Infineon/CYPRESS CY7C1420KV18-250BZXC

The CY7C1418KV18, and CY7C1420KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. On CY7C1418KV18 and CY7C1420KV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1418KV18 and two 36-bit words in the case of CY7C1420KV18 sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

• 36-Mbit density (2M x 18, 1M x 36)
• 1333 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing ❐SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Synchronous internally self-timed writes
• DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH
• Operates similar to DDR-I device with 1 cycle read latency when DOFF is asserted LOW
• 1.8 V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4 V to VDD)
• Supports both 1.5 V and 1.8 V IO supply
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Offered in both Pb-free and non Pb-free packages
• JTAG 1149.1 compatible test access port
• Phase locked loop (PLL) for accurate data placement