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TI SN74AVCH2T45YZPR

Manufacturer
TI
MPN
SN74AVCH2T45YZPR
LCSC Part #
C2879461
Packaging
DSBGA-8
Customer #
Key Attributes
2-Bit, 2-Supply, Bus Transceiver with Configurable Level-Shifting and Translation and 3-State Outputs
DatasheetTI SN74AVCH2T45YZPR
RoHS Compliance2 documents available
In-Stock: 500
500 In stock, ships now
Minimum: 1Multiple: 1Sales Unit: Piece
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QtyUnit PriceTotal Amount
1+$ 0.7968$ 0.80
10+$ 0.7156$ 7.16
30+$ 0.6702$ 20.11
100+$ 0.6183$ 61.83
500+$ 0.5956$ 297.80
1,000+$ 0.5858$ 585.80
Standard Packaging3000/Full Reel
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Translators, Level Shifters
ManufacturerTI
PackagingDSBGA-8
output typeTri-State
Interface-
Output Signal-
Input Signal-
Operating Temperature-40℃~+85℃
Data Rate500Mbps
Number of Elements1
Channel TypeBidirectional
FeaturesPower-off protection;Output enable high-impedance
Voltage - Supply1.2V~3.6V;1.2V~3.6V
Number of Circuits2
Current - Output High(IOH)-
Current - Output Low(IOL)-
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Introduction

AI Translation

This 2-bit non-inverting bus transceiver uses two separate configurable power rails. The A port tracks VCCA and supports any supply voltage in the range of 1.2V to 3.6V. The B port tracks VCCB and supports any supply voltage in the range of 1.2V to 3.6V. This enables universal low-voltage bidirectional translation and level shifting between 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVCH2T45 is designed for asynchronous communication between two data buses. The logic level applied to the direction control (DIR pin) input activates either the B port or A port outputs. When the B port outputs are activated, the device transmits data from the A bus to the B bus; when the A port outputs are activated, the device transmits data from the B bus to the A bus.

The SN74AVCH2T45 features an active bus-hold circuit that holds unused or undriven inputs at a valid logic state. The use of pull-up or pull-down resistors on the bus-hold circuit is not recommended.

This device is designed for partial power-down applications using Ioff. The Ioff circuit disables the outputs to prevent damaging reverse current flow through the device when it is powered down. The VCC isolation feature ensures that both outputs are in a high-impedance state when either VCC input is grounded. The bus-hold circuit on the powered side remains active at all times.

The active bus-hold circuit holds unused or undriven inputs at a valid logic state. NanoFree packaging technology represents a significant breakthrough in IC packaging concepts, using the silicon die itself as the package.

Features

AI Translation
  • NanoFree package
  • VCC isolation
  • 2-rail design
  • I/O tolerant to 4.6V
  • Partial power-down mode operation
  • Bus-hold data inputs
  • Maximum data rate:
    • 500Mbps (1.8V to 3.3V)
    • 320Mbps (<1.8V to 3.3V)
    • 320Mbps (level translation to 2.5V or 1.8V)
    • 280Mbps (level translation to 1.5V)
    • 240Mbps (level translation to 1.2V)
  • Latch-up performance exceeds 100mA per JESD78 Class II
  • ESD protection exceeds JESD22 specifications

Applications

AI Translation
  • Smartphone
  • Servers
  • Desktop PCs and Notebooks
  • Other Portable Devices