RENESAS 9DBV0641AKLF
| Manufacturer | |
| MPN | 9DBV0641AKLF |
| LCSC Part # | C1519964 |
| Packaging | VFQFPN-40-EP(5x5) |
| Customer # | |
| Key Attributes | 1.7V~1.9V 200MHz 6 VFQFPN-40-EP(5x5) Clock Generators, PLLs, Frequency Synthesizers RoHS |
| Datasheet | RENESAS 9DBV0641AKLF |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | RENESAS | |
| Packaging | VFQFPN-40-EP(5x5) | |
| Operating Temperature | 0℃~+70℃ | |
| Voltage - Supply | 1.7V~1.9V | |
| Output Frequency(Max) | 200MHz | |
| Number of Outputs | 6 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | RENESAS | |
| Packaging | VFQFPN-40-EP(5x5) | |
| Operating Temperature | 0℃~+70℃ |
| Type | Description | |
|---|---|---|
| Voltage - Supply | 1.7V~1.9V | |
| Output Frequency(Max) | 200MHz | |
| Number of Outputs | 6 |
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Introduction
AI Translation
The 9DBV0641 is a member of IDT's 1.8V Very-Low-Power (VLP) PCIe family. It has integrated output terminations providing Z0 = 100 ohms for direct connection to 100ohm transmission lines. The device has 6 output enables for clock management and 3 selectable SMBus addresses.
Features
AI Translation
- 6 - 1-200 MHz Low-Power (LP) HCSL DIF pairs w/Z0=100Ω
- Direct connection to 100ohm transmission lines; saves 24 resistors compared to standard PCIe devices
- 55mW typical power consumption in PLL mode; minimal power consumption
- Outputs can optionally be supplied from any voltage between 1.05 and 1.8V; maximum power savings
- OE# pins; support DIF power management
- HCSL compatible differential input; can be driven by common clock sources
- Spread Spectrum tolerant; allows reduction of EMI
- Programmable Slew rate for each output; allows tuning for various line lengths
- Programmable output amplitude; allows tuning for various application environments
- Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
- Outputs blocked until PLL is locked; clean system start-up
- Configuration can be accomplished with strapping pins; SMBus interface not required for device control
- 3.3V tolerant SMBus interface works with legacy controllers
- Space saving 40-pin 5x5mm VFQFPN; minimal board space
- 3 selectable SMBus addresses; multiple devices can easily share an SMBus segment
Applications
AI Translation
- 1.8V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | RENESAS | |
| Packaging | VFQFPN-40-EP(5x5) | |
| Operating Temperature | 0℃~+70℃ | |
| Voltage - Supply | 1.7V~1.9V | |
| Output Frequency(Max) | 200MHz | |
| Number of Outputs | 6 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | RENESAS | |
| Packaging | VFQFPN-40-EP(5x5) | |
| Operating Temperature | 0℃~+70℃ |
| Type | Description | |
|---|---|---|
| Voltage - Supply | 1.7V~1.9V | |
| Output Frequency(Max) | 200MHz | |
| Number of Outputs | 6 |
Help & FeedbackShow similar products (0) >
Introduction
AI Translation
The 9DBV0641 is a member of IDT's 1.8V Very-Low-Power (VLP) PCIe family. It has integrated output terminations providing Z0 = 100 ohms for direct connection to 100ohm transmission lines. The device has 6 output enables for clock management and 3 selectable SMBus addresses.
Features
AI Translation
- 6 - 1-200 MHz Low-Power (LP) HCSL DIF pairs w/Z0=100Ω
- Direct connection to 100ohm transmission lines; saves 24 resistors compared to standard PCIe devices
- 55mW typical power consumption in PLL mode; minimal power consumption
- Outputs can optionally be supplied from any voltage between 1.05 and 1.8V; maximum power savings
- OE# pins; support DIF power management
- HCSL compatible differential input; can be driven by common clock sources
- Spread Spectrum tolerant; allows reduction of EMI
- Programmable Slew rate for each output; allows tuning for various line lengths
- Programmable output amplitude; allows tuning for various application environments
- Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
- Outputs blocked until PLL is locked; clean system start-up
- Configuration can be accomplished with strapping pins; SMBus interface not required for device control
- 3.3V tolerant SMBus interface works with legacy controllers
- Space saving 40-pin 5x5mm VFQFPN; minimal board space
- 3 selectable SMBus addresses; multiple devices can easily share an SMBus segment
Applications
AI Translation
- 1.8V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
C1519964 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

