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SILICON LABS C8051F040-GQR

Manufacturer
SILICON LABS
MPN
C8051F040-GQR
LCSC Part #
C14478
Packaging
TQFP-100(14x14)
Customer #
Key Attributes
25 MIPS, 64 kB Flash, 12-Bit ADC, 100-Pin Mixed-Signal McU
DatasheetSILICON LABS C8051F040-GQR
RoHS Compliance1 documents available
Alternative Parts5
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microcontrollers
ManufacturerSILICON LABS
PackagingTQFP-100(14x14)
DAC (Bit)10bit;12bit
ADC (Bit)8bit;12bit
Number of I/O64
Operating Temperature-40℃~+85℃
Program Memory TypeFLASH
Voltage - Supply2.7V~3.6V
EEPROM-
Program Storage Size64KB
CPU Core51 Series
Core Size8 Bit
CPU Maximum Speed25MHz
Oscillator TypeBuilt-in
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Features

AI Translation
  • ±1 LSB INL; guaranteed monotonic
  • Programmable throughput up to 100 ksps
  • 13 external inputs; programmable as single-ended or differential
  • Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
  • Data-dependent windowed interrupt generator
  • Built-in temperature sensor (±3 °C)
  • 60 V common mode input range
  • Offset adjust from -60 to +60 V
  • 16 gain settings from 0.05 to 16
  • Programmable throughput up to 500 ksps
  • 8 external inputs; programmable as single-ended or differential
  • Programmable amplifier gain: 4, 2, 1, 0.5
  • On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required)
  • Provides breakpoints, single stepping, watchpoints, stack monitor, program trace memory
  • Inspect/modify memory and registers
  • Superior performance to emulation systems using ICE-chips, target pods, and sockets
  • IEEE1149.1 compliant boundary scan
  • Pipelined instruction architecture; executes 70% of in system clocks
  • Up to 25 MIPS throughput with 25 MHz system clock
  • Expanded interrupt handler
  • 4352 bytes data RAM
  • 64 kB Flash; in-system programmable in 512-byte sectors (512 bytes are reserved)
  • External parallel data memory interface
  • 32 message objects
  • ”Mailbox" implementation only interrupts CPU when needed
  • 64 port I/O; all are 5 V tolerant
  • Hardware SMBus (I²C compatible), SPI, and two UART serial ports available concurrently
  • Programmable 16-bit counter array with 6 capture/compare modules
  • 5 general-purpose 16-bit counter/timers
  • Dedicated watchdog timer; bidirectional reset
  • Real-time clock mode using timer 3 or PCA
  • Internal programmable 2% oscillator: up to 25 MHz
  • External oscillator: Crystal, RC, C, or Clock
  • 100-pin TQFP (standard lead and lead-free packages)