Intel/Altera RGE7500PL

The Intel E7500 chipset includes the Memory Controller Hub (MCH), Intel 82801CA I/O Controller Hub 3-S (ICH3-S), and Intel 82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2). Intel E7500 MCH Overview:

• Processor System Interface
• Main Memory Interface
• Hub Interface_A (HI_A)
• Hub Interface_B-D (HI_B-D)
• MCH Clock
• SMBus Interface

Signal descriptions cover system bus interface signals, DDR Channel A signals, DDR Channel B signals, hub interface signals, clocks, reset, power and other miscellaneous signals, as well as pin states during and after reset.

Register descriptions include register terminology, platform configuration, general routing configuration access (including standard PCI configuration mechanism, logical PCI Bus 0 configuration mechanism, primary PCI downstream configuration mechanism, HI_B/HI_C/HI_D bus configuration mechanisms), sticky registers, I/O mapped registers, DRAM controller registers (including various registers such as Vendor Identification Register, Device Identification Register, etc.), and DRAM controller error reporting registers (including various error reporting-related registers).