Infineon CYT2BL3CAAQ0AZEGS

CYT2BL is part of the TRAVEO T2G microcontroller family, targeting systems such as automotive body control units. This family employs an Arm Cortex-M4F CPU for main processing, paired with an Arm Cortex-M0+ CPU for peripheral and safety processing. These devices integrate embedded peripherals supporting CAN FD, LIN, and CXPI protocols. TRAVEO T2G devices are manufactured using an advanced 40nm process. CYT2BL integrates low-power flash memory, multiple high-performance analog and digital peripherals, and supports the creation of a safe computing platform.

• Dual CPU subsystem: 160-MHz (max) 32-bit Arm Cortex-M4F CPU with single-cycle multiply and single-precision FPU; 100-MHz (max) 32-bit Arm Cortex-M0+ CPU with single-cycle multiply; hardware-level inter-processor communication; three DMA controllers.
• Integrated memory: 4160 KB code flash and 128 KB work flash with read-while-write and single/dual bank modes; 512 KB SRAM with configurable retention granularity.
• Cryptographic engine: enhanced secure hardware extension and hardware security module; secure boot and authentication; AES, 3DES, vector unit (RSA and ECC asymmetric key encryption), SHA-1/2/3, CRC, TRNG, PRNG, and Galois/Counter Mode.
• ASIL-B functional safety: MPU, shared memory protection unit, peripheral protection unit, watchdog timer, multi-counter watchdog timer, brownout detector, power-on detector, overvoltage detection, clock monitor, and hardware ECC for all safety-critical memories (SRAM, flash).
• 2.7-V to 5.5-V low-power operation: low-power active, sleep, low-power sleep, deep sleep, and hibernate modes for fine-grained power management; configurable brownout detection options.
• Wake-up support: up to 2 pins wake from hibernate mode; up to 152 GPIO pins wake from sleep mode; event generator, SCB, watchdog timer, and RTC alarm wake from deep sleep mode.
• Clock sources: internal main oscillator, internal low-speed oscillator, external crystal oscillator, watch crystal oscillator, PLL, and FLL.
• Communication interfaces: up to eight CAN FD channels; up to eight runtime-reconfigurable SCB channels, each configurable as I2C, SPI, or UART; up to 12 independent LIN channels; up to four CXPI channels with data rates up to 20 kbps.
• Timers: up to 75 16-bit and eight 32-bit timer/counter PWM modules; up to 11 event generator timers supporting cyclic wake from deep sleep.
• RTC: year/month/day, day-of-week, hour:minute:second fields; 12-hour and 24-hour formats; automatic leap year correction.
• I/O: up to 152 programmable I/Os; two I/O types: standard GPIO and enhanced GPIO.
• Regulator: generates 1.1-V nominal core supply from 2.7-V to 5.5-V input supply; two regulator types: deep sleep and core internal.
• Programmable analog: three SAR ADCs supporting up to 67 external channels; 12-bit resolution and up to 1 Msps per ADC; up to six internal analog inputs per ADC.

• Body Control Unit