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Nexperia 74HC280D,653
| Manufacturer | |
| MPN | 74HC280D,653 |
| LCSC Part # | C546802 |
| Packaging | SOIC-14 |
| Customer # | |
| Key Attributes | 9-bit odd/even parity generator/checker |
| Datasheet | Nexperia 74HC280D,653 |
| RoHS Compliance | 1 documents available |
| Alternative Parts | 9 |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Parity Generators and Checkers | |
| Manufacturer | Nexperia | |
| Packaging | SOIC-14 | |
| Logic Type | Parity Generator/Checker | |
| Voltage - Supply | 2V~6V | |
| Operating Temperature | -40℃~+125℃ | |
| Series | 74HC | |
| Number of Bits per Element | 9 | |
| Features | Odd parity generation;Even parity generation;Simultaneous odd/even parity output |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Parity Generators and Checkers | |
| Manufacturer | Nexperia | |
| Packaging | SOIC-14 | |
| Logic Type | Parity Generator/Checker | |
| Voltage - Supply | 2V~6V |
| Type | Description | |
|---|---|---|
| Operating Temperature | -40℃~+125℃ | |
| Series | 74HC | |
| Number of Bits per Element | 9 | |
| Features | Odd parity generation;Even parity generation;Simultaneous odd/even parity output |
Introduction
The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs are HIGH. Expansion to larger word sizes is accomplished by tying the even outputs (PE) of up to nine parallel devices to the final stage data inputs. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Features
- Word-length easily expanded by cascading
- Generates either odd or even parity for nine data bits
- Wide supply voltage range from 2.0 to 6.0 V
- Input levels: For 74HC280: CMOS level For 74HCT280: TTL level
- CMOS low power dissipation
- High noise immunity
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0V to 6.0 V)
- ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 1.2046 | $ 1.20 |
| 10+ | $ 1.0478 | $ 10.48 |
| 30+ | $ 0.9686 | $ 29.06 |
| 100+ | $ 0.891 | $ 89.10 |
| 500+ | $ 0.8445 | $ 422.25 |
| 1,000+ | $ 0.8212 | $ 821.20 |
Standard Packaging2500/Full Reel | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Parity Generators and Checkers | |
| Manufacturer | Nexperia | |
| Packaging | SOIC-14 | |
| Logic Type | Parity Generator/Checker | |
| Voltage - Supply | 2V~6V | |
| Operating Temperature | -40℃~+125℃ | |
| Series | 74HC | |
| Number of Bits per Element | 9 | |
| Features | Odd parity generation;Even parity generation;Simultaneous odd/even parity output |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Parity Generators and Checkers | |
| Manufacturer | Nexperia | |
| Packaging | SOIC-14 | |
| Logic Type | Parity Generator/Checker | |
| Voltage - Supply | 2V~6V |
| Type | Description | |
|---|---|---|
| Operating Temperature | -40℃~+125℃ | |
| Series | 74HC | |
| Number of Bits per Element | 9 | |
| Features | Odd parity generation;Even parity generation;Simultaneous odd/even parity output |
Introduction
The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs are HIGH. Expansion to larger word sizes is accomplished by tying the even outputs (PE) of up to nine parallel devices to the final stage data inputs. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Features
- Word-length easily expanded by cascading
- Generates either odd or even parity for nine data bits
- Wide supply voltage range from 2.0 to 6.0 V
- Input levels: For 74HC280: CMOS level For 74HCT280: TTL level
- CMOS low power dissipation
- High noise immunity
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0V to 6.0 V)
- ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
C546802 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
Alternative Parts
| MPN | Manufacturer | Packaging | Availability | Unit Price | ||
|---|---|---|---|---|---|---|
| SN74HC280DR(LX) | lingxingic | SOP-14 | 2,025 | $0.1837 $0.1933 | ||
| SN74LS280DR(LX) | lingxingic | SOP-14 | 492 | $0.4105 $0.4321 | ||
| CD74HC280M96 | TI | SOIC-14 | 0 | $ 0.5194 | ||
| CD74AC280M96 | TI | SOIC-14 | 0 | $ 0.5676 | ||
| CD74ACT280M96 | TI | SOIC-14 | 0 | $ 0.5914 | ||
| 74ACT11286D | TI | SOIC-14 | 0 | $ 3.5454 | ||
| 74HCT280D,653 | Nexperia | SOIC-14 | 0 | $ 0.3243 | ||
| SN74F280BDR | TI | SOIC-14 | 0 | $ 0.3541 | ||
| 74F280SC | TI | SOIC-14 | 0 | $ 0.2429 |