NXP MPC8309CVMAGDCA

The MPC8309 is a cost-effective, highly integrated communications processor that addresses the requirements of several networking applications, including residential gateways, modem/routers, industrial control, and test and measurement applications. The MPC8309 extends current PowerQUICC offerings, adding higher CPU performance, additional functionality, and faster interfaces, while addressing the requirements related to time-to-market, price, power consumption, and board real estate. The MPC8309 incorporates the e300c3 (MPC603e-based) core built on Power Architecture technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The MPC8309 also includes a 32-bit PCI controller, two DMA engines and a 16/32-bit DDR2 memory controller with 8-bit ECC. A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8309. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the unified communication controllers (UCCs). Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps MII/RMII Ethernet, HDLC and TDM. In summary, the MPC8309 provides users with a highly integrated, fully programmable communications processor. This helps to ensure that a low-cost system solution can be quickly developed and offers flexibility to accommodate new standards and evolving system requirements.

• e300c3 Power Architecture processor core
  • Enhanced version of the MPC603e core
  • High-performance, superscalar processor core with a four-stage pipeline and low interrupt latency times
  • Floating-point, dual integer units, load/store, system register, and branch processing units
  • 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities
  • Dynamic power management
  • Enhanced hardware program debug features
  • Software-compatible with Freescale processor families implementing Power Architecture technology
  • Separate PLL that is clocked by the system bus clock
  • Performance monitor
• QUICC Engine block
  • 32-bit RISC controller for flexible support of the communications peripherals
    • One clock per instruction
    • Separate PLL for operating frequency that is independent of system’s bus and e300 core frequency for power and performance optimization
    • 32-bit instruction object code
    • Executes code from internal IRAM
    • 32-bit arithmetic logic unit (ALU) data path
    • Modular architecture allowing for easy functional enhancements
    • Slave bus for CPU access of registers and multiuser RAM space
    • 48 Kbytes of instruction RAM
    • 16 Kbytes of multiuser data RAM
    • Serial DMA channel for receive and transmit on all serial channels
  • Five unified communication controllers (UCCs) supporting the following protocols and interfaces
    • 10/100 Mbps Ethernet/IEEE Std. 802.3 through MII and RMII interfaces
    • IEEE Std. 1588 support
    • HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8)
    • HDLC Bus (bit rate up to 10 Mbps)
    • Asynchronous HDLC (bit rate up to 2 Mbps)
    • Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each running at 64 kbps
• DDR SDRAM memory controller
  • Programmable timing supporting DDR2 SDRAM
  • Integrated SDRAM clock generation
  • Supports 8-bit ECC
  • 16/32-bit data interface, up to 333-MHz data rate
  • 14 address lines
  • The following SDRAM configurations are supported
    • Up to two physical banks (chip selects), 512-Mbyte addressable space for 32 bit data interface
    • 64-Mbit to 2-Gbit devices with x8/x16/x32 data ports (no direct x4 support)
  • One 16-bit device or two 8-bit devices on a 16-bit bus, or two 16-bit devices or four 8-bit devices on a 32-bit bus
  • Support for up to 16 simultaneous open pages for DDR2
  • Two clock pair to support up to 4 DRAM devices
  • Supports auto refresh
  • On-the-fly power management using CKE
• Enhanced local bus controller (eLBC)
  • Multiplexed 26-bit address and 8-/16-bit data operating at up to 66 MHz
  • Eight chip selects supporting eight external slaves
    • Four chip selects dedicated
    • Four chip selects offered as multiplexed option
  • Supports boot from parallel NOR Flash and parallel NAND Flash
  • Supports programmable clock ratio dividers
  • Up to eight-beat burst transfers
  • 16- and 8-bit ports, separate LWE for each 8 bit
  • Three protocol

• residential gateways
• modem/routers
• industrial control
• test and measurement applications