Nanya Tech NT5CC64M16GP-DI

The 1Gb Double-Data-Rate-3 (DDR3(L)) G-die DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 1Gb chip is organized as 16Mbit x8 I/Osx8 banks or 8Mbit x 16 I/Osx8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 2133 Mb/pin/sec for general applications. The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V±0.075V or 1.35V -0.067/+0.1V power supply and are available in BGA packages.

The DDR3(L) SDRAM is a high-speed dynamic random access memory internally configured as an eight-bank DRAM. The DDR3(L) SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3(L) SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR3(L) SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence.

• 8n Prefetch Architecture - Differential Clock(CK/CK) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM
• Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes
• Partial Array Self Refresh (PASR)
• Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm±1%)
• Write Leveling via MR settings 6 - Read Leveling via MPR
• Interface and Power Supply - SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V) - SSTL_135 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)
• Speed Grade (CL-TRCD-TRP) 2
  • 2133 Mbps / 14-14-14
  • 1866 Mbps / 13-13-13
  • 1600 Mbps / 11-11-11, 10-10-10
• Temperature Range (Tc)
  • Commercial Grade =0℃~95℃
  • Quasi Industrial Grade (-T)=-40℃~95℃
  • Industrial Grade (-1)=-40℃~95℃
  • Automotive Grade 2 (-H)=-40℃~105℃
  • Automotive Grade 3 (-A)=-40℃~95℃
• Programmable Functions
  • CAS Latency (6/7/8/9/10/11/13/14)
  • CAS Write Latency (5/6/7/8/9/10)
  • Additive Latency (0/CL-1/CL-2)
  • Write Recovery Time (5/6/7/8/10/12/14/16)
  • Burst Type (Sequential/Interleaved)
  • Burst Length (BL8/BC4/BC4 or 8 on the fly)
  • Self Refresh Temperature Range(Normal/Extended)
  • Output Driver Impedance (34/40)
  • On-Die Termination of Rtt_Nom(20/30/40/60/120)
  • On-Die Termination of Rtt_WR(60/120)
  • Precharge Power Down (slow/fast)