TI SNJ54LS590FK
| Fabricante | |
| N.º de pieza fab. | SNJ54LS590FK |
| Nº LCSC | C3828091 |
| Emb. | LCC-20(8.9x8.9) |
| Número de Cliente | |
| Atrib. clave | Rising Edge 1 20MHz LCC-20(8.9x8.9) Counters, Dividers |
| Hoja de Datos | TI SNJ54LS590FK |
Especificaciones del Producto
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Fabricante | TI | |
| Emb. | LCC-20(8.9x8.9) | |
| Logic Family | LS | |
| Voltage - Supply | 4.5V~5.5V | |
| Direction | - | |
| Trigger Type | Rising Edge | |
| Timing | - | |
| Reset | - | |
| Operating Temperature | -55℃~+125℃ | |
| Number of Elements | 1 | |
| Propagation Delay | 22ns@5V,30pF;30ns@5V,30pF | |
| Count Rate | 20MHz | |
| Features | Reset function;Cascade counter |
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Fabricante | TI | |
| Emb. | LCC-20(8.9x8.9) | |
| Logic Family | LS | |
| Voltage - Supply | 4.5V~5.5V | |
| Direction | - | |
| Trigger Type | Rising Edge |
| Tipo | Descripción | |
|---|---|---|
| Timing | - | |
| Reset | - | |
| Operating Temperature | -55℃~+125℃ | |
| Number of Elements | 1 | |
| Propagation Delay | 22ns@5V,30pF;30ns@5V,30pF | |
| Count Rate | 20MHz | |
| Features | Reset function;Cascade counter |
Descripción
These devices each contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features a direct clear input CCLR and a count enable input CCKEN. For cascading, a ripple carry output ACO (overline) is provided. Expansion is easily accomplished for two stages by connecting RcO of the first stage to CCKEN of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to CCK of the following stage. Both the counter and register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the counter state will always be one count ahead of the register. Internal circuitry prevents clocking from the clock enable.
Características
- 8-Bit Counter with Register
- Parallel Register Outputs Choice of 3-State ('LS590) or Open Collector ('LS591)
- Register Outputs Guaranteed Counter Frequency: DC to 20 MHz
| Cant. | Prec. unit.(Solo como referencia) | Importo total |
|---|---|---|
| 1+ | $ 132.5539 | $ 132.55 |
| 200+ | $ 51.2976 | $ 10259.52 |
| 500+ | $ 49.4949 | $ 24747.45 |
| 1,000+ | $ 48.6039 | $ 48603.90 |
Encapsulado Estándar50/Full Tube | ||
Especificaciones del Producto
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Fabricante | TI | |
| Emb. | LCC-20(8.9x8.9) | |
| Logic Family | LS | |
| Voltage - Supply | 4.5V~5.5V | |
| Direction | - | |
| Trigger Type | Rising Edge | |
| Timing | - | |
| Reset | - | |
| Operating Temperature | -55℃~+125℃ | |
| Number of Elements | 1 | |
| Propagation Delay | 22ns@5V,30pF;30ns@5V,30pF | |
| Count Rate | 20MHz | |
| Features | Reset function;Cascade counter |
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Fabricante | TI | |
| Emb. | LCC-20(8.9x8.9) | |
| Logic Family | LS | |
| Voltage - Supply | 4.5V~5.5V | |
| Direction | - | |
| Trigger Type | Rising Edge |
| Tipo | Descripción | |
|---|---|---|
| Timing | - | |
| Reset | - | |
| Operating Temperature | -55℃~+125℃ | |
| Number of Elements | 1 | |
| Propagation Delay | 22ns@5V,30pF;30ns@5V,30pF | |
| Count Rate | 20MHz | |
| Features | Reset function;Cascade counter |
Descripción
These devices each contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features a direct clear input CCLR and a count enable input CCKEN. For cascading, a ripple carry output ACO (overline) is provided. Expansion is easily accomplished for two stages by connecting RcO of the first stage to CCKEN of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to CCK of the following stage. Both the counter and register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the counter state will always be one count ahead of the register. Internal circuitry prevents clocking from the clock enable.
Características
- 8-Bit Counter with Register
- Parallel Register Outputs Choice of 3-State ('LS590) or Open Collector ('LS591)
- Register Outputs Guaranteed Counter Frequency: DC to 20 MHz
Cumplimiento & Códigos de Exportación
| Tipo | Detalles |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Tipo | Detalles |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Tipo | Detalles |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |