TI CD4515BM96

CD4514B and -CD4515B consist of a 4-bit :strobed latch and a 4-to-16-ine decoder. The latches hold the last input data presented prior to the strobe transition from 1 to 0. Inhibit control allows all outputs to be placed at 0(CD4514B) or 1(CD4515B) regardless of the state of the data or strobe inputs. The decode .truth table indicates all combi. nations of data inputs and appropriate selected outputs.

• Strobed input latch
• Inhibit control
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 μA at 18 V over full package-temperature range; 100 Ω at 18 V and 25℃
• Noise margin (over full package temperature range): 1 V at VDd = 5V, 2 V at VDd = 10 V, 2.5 V at VDD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Standardized, symmetrical output characteristics
• Meets all requirements of JEDEC Tentative Standard No. 13B; "Standard Specifications for Description of ∠B′ Series CMOS Devices"

• Digital multiplexing
• Address decoding
• Hexadecimal/BCD decoding
• Program-counter decoding
• Control decoder