RENESAS R5F11NLFAFB#10

This device integrates an analog front end comprising a 24-bit ΔΣ ADC with a programmable gain instrumentation amplifier, an amplifier unit, and a 12-bit DAC. It also features an external signal sampler, a sample output timing detector, and an integrated LCD controller and driver. The device is built on a true low-power platform, achieving operating current as low as 70.8 μA/MHz, with 0.68 μA in shutdown mode (RTC2 plus LVD). Its operating voltage range spans 1.8 V to 5.5 V, with 64 to 128 KB flash memory, delivering 33 DMIPS performance at 24 MHz, making it suitable for healthcare and flow meter applications.

• Ultra-low power consumption technology
• Operating voltage range: VDD = 2.4 V to 5.5 V (10-bit SAR ADC: 2.4 V to 5.5 V, analog front-end operating voltage: 2.7 V to 5.5 V), VDD = 1.8 V to 5.5 V
• HALT mode, STOP mode, and SNOOZE mode support
• RL78 CPU core with CISC architecture and 3-stage pipeline
• Minimum instruction execution time adjustable from high-speed (0.04167 µs at 24 MHz high-speed on-chip oscillator clock) to ultra-low-speed (30.5 µs at 32.768 kHz subsystem clock)
• Multiply/divide and multiply-accumulate instruction support
• 1 MB address space
• General-purpose registers: 8-bit registers × 8 × 4 banks
• On-chip RAM: 5.5 KB or 8 KB
• Code flash memory: 64 to 128 KB, block size 1 KB
• Block erase/rewrite protection, on-chip debug, and self-programming functions
• Data flash memory: 4 KB with background operation support, typical endurance 1,000,000 erase/write cycles, rewrite voltage VDD = 2.4 V to 5.5 V or 1.8 V to 5.5 V
• High-speed on-chip oscillator: selectable frequencies of 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz, high accuracy ±1.0%
• Operating ambient temperature: TA = -40°C to +85°C
• Power management and reset functions, including on-chip power-on-reset circuit and on-chip voltage detector
• Data transfer controller supporting normal transfer mode, repeat transfer mode, and block transfer mode; activatable by 35 interrupt sources with chained transfer capability
• Event link controller linking 18 to 26 types of event signals to designated peripheral functions
• Serial interfaces: 3-channel CSI, 3-channel UART, 4-channel I2C/simplified I2C, and 1-channel SIUART
• Timers: 8-channel 16-bit timer array unit, 2-channel timers, 2 or 6-channel 8-bit timers, 1-channel 12-bit interval timer, 1-channel RTC2, and 1-channel watchdog timer
• LCD controller/driver with switchable internal voltage boost, capacitor split, and external resistor voltage divider methods
• Analog front-end power supply circuit including AFE reference power supply, LDO regulator for internal circuit power, and LDO regulator for sensor power
• 24-bit ΔΣ ADC with programmable gain instrumentation amplifier, SINAD of 85 dB, output data rate of 488 sps to 15.625 ksps in normal mode and 61 sps to 1.953 ksps in low-power mode
• Amplifier unit: 1-channel programmable gain instrumentation amplifier and 1-channel rail-to-rail op-amp
• DAC: 1-channel 8-bit resolution R-2R ladder DAC and 1-channel 12-bit resolution R-2R ladder DAC
• 10-bit SAR ADC with 3 analog input channels, internal reference voltage, and temperature sensor
• I/O ports: 29 to 63, configurable as N-channel open-drain, TTL input buffer, and on-chip pull-up resistor
• On-chip clock output/buzzer output controller
• On-chip BCD correction circuit