NXP MPC8343VRAGDB

The MPC8343EA PowerQUICC II Pro is the next-generation PowerQUICC II integrated host processor. The MPC8343EA incorporates a processor core built on Power Architecture technology, along with system logic for networking, storage, and general-purpose embedded applications. For processor features, refer to the MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual. The information in this document applies to silicon revision 3.x and later (i.e., orderable part numbers ending in A or B). For information on silicon revision 1.1 and earlier, refer to the MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications. For details on determining the silicon revision level, see Section 22.1, "Full Part Numbers Covered by This Document." This section provides a high-level overview of the device features.

• Integrated PowerPC e300 processor core, up to 400 MHz operating frequency
• High-performance superscalar processor core
• Includes floating-point, integer, load/store, system register, and branch processing units
• 32-Kbyte instruction cache, 32-Kbyte data cache
• L1 cache partial region lockable
• Dynamic power management
• Software compatible with other Freescale processor families implementing Power Architecture technology
• Integrated DDR1/DDR2 SDRAM memory controller
• Programmable timing support for DDR1 and DDR2 SDRAM
• 32-bit data interface, up to 266 MHz data rate
• Up to 4 physical memory banks (chip selects), each independently addressable up to 1 Gbyte
• Supports DRAM chip configurations from 64 Mbit to 1 Gbit with ×8/×16 data ports
• Full ECC support
• Up to 16 simultaneously open pages (up to 32 for DDR2)
• Contiguous or non-contiguous memory map support
• Read-modify-write operation support
• Sleep mode with SDRAM self-refresh support
• Auto-refresh support
• Dynamic power management via CKE
• Registered DIMM support
• DDR1: 2.5-V SSTL2-compatible I/O; DDR2: 1.8-V SSTL2-compatible I/O
• Integrated dual three-speed (10/100/1000) Ethernet controllers (TSEC)
• Dual-controller design compliant with IEEE 802.3, 802.3u, 802.3x, 802.3z, and 802.3ac
• Multiple Ethernet physical interface support: 1000 Mbps IEEE Std 802.3 RGMII, IEEE Std 802.3z RTBI full-duplex; 10/100 Mbps IEEE Std 802.3 MII full-duplex and half-duplex
• Buffer descriptor backward compatible with MPC8260 and MPC860T 10/100 programming model
• 9.6-Kbyte jumbo frame support
• RMON statistics support
• 2-Kbyte transmit FIFO and 2-Kbyte receive FIFO integrated per TSEC module
• MII management interface for control and status query
• Programmable CRC generation and checking
• Integrated PCI interface compliant with PCI Specification Revision 2.3
• 32-bit PCI data interface, up to 66 MHz operating frequency
• PCI 3.3-V compatible
• PCI host bridge capability
• PCI slave mode support
• PCI-to-memory and memory-to-PCI streaming support
• Memory prefetch for PCI read access with delayed read transaction support
• Processor-to-PCI and PCI-to-memory write transfer support
• On-chip arbitration supporting 5 PCI masters
• Full PCI address space access support
• Parity support
• Optional hardware-enforced coherency support
• Address translation unit for host-to-peripheral address mapping
• Target dual address cycle support
• Internal configuration registers accessible from PCI
• Security engine optimized for all algorithms related to IPSec, SSL/TLS, SRTP, IEEE Std 802.11i, iSCSI, and IKE processing
• Security engine includes four encryption channels, one controller, and a set of cryptographic execution units (EUs)
• Public Key Execution Unit (PKEU): RSA and Diffie-Hellman algorithm support; programmable field size up to 2048 bits; elliptic curve cryptography support; F2m and F(p) mode support; programmable field size up to 511 bits
• Data Encryption Standard Execution Unit (DEU): DES and 3DES algorithm support; 3DES dual-key (K1, K2) or triple-key (K1, K2, K3) support; ECB and CBC mode support for both DES and 3DES
• Advanced Encryption Standard Unit (AESU): Rijndael symmetric key cipher implementation; 128-bit, 192-bit, and 256-bit key length support; ECB, CBC, CCM, and counter (CTR) mode support
• XOR parity generation accelerator for RAID applications
• ARC Four Execution Unit (AFEU): RC4-compatible stream cipher support; 40- to 128-bit programmable key support
• Message Digest Execution Unit (MDEU): SHA with 160-bit, 224-bit, or 256-bit message digest support; MD5 with 128-bit message digest support; HMAC support for both algorithms
• Integrated random number generator (RNG)
• Four encryption channels, each supporting multi-command descriptor chaining; static and/or dynamic cryptographic EU allocation via integrated controller; 256-byte buffer per EU for large data flow control

• Networking
• Storage
• General-purpose embedded applications