TI SN74LS610N

The LS610 through 'LS613 memory mapper ICs integrate a 4-line to 16-line decoder, a 16-word × 12-bit RAM, a 16-channel 2-line to 1-line multiplexer, and other auxiliary circuits on a single monolithic chip. The 'LS610 and 'LS611 additionally incorporate 12 latches with enable control. The memory mapper is designed to extend the memory addressing capability of a microprocessor by 8 bits. Four bits of the memory address bus can be used to select one of 16 mapping registers, each storing 12 bits; these 12 bits are presented to the system memory address bus through the mapping output buffers, along with the memory address bits not used by the CPU. However, without reloading the mapping registers, the addressable memory space remains the same as when the memory mapper is not used. Only by periodically reloading the mapping registers from the data bus can the addressable memory space be expanded. This architecture supports the use of 16 pages of memory without reloading, with 2^(n - 4) registers per page (where n = the number of address bits provided by the CPU). These devices have four operating modes: Read, Write, Map, and Pass-Through. When Chip Select (CS) is low, data can be read from or loaded into the mapping register selected by the Register Select inputs (RS0 thru RS3), under R/W control. Data input/output is performed via data bus lines D0 thru D7. When CS is high and MM (Map Mode control) is low, the map operation is performed, and the contents of the mapping register selected by the Map Address inputs (MA0 thru MA3) are output. The output stages of the 'LS612 and 'LS613 are transparent in this mode, while the 'LS610 and 'LS611 outputs can be either transparent or latched. When both CS and MM are high (Pass-Through mode), the address bits on Map Address inputs MA0 thru MA3 appear at M08–M011 respectively (assuming appropriate latch control), and all other bit positions of the map outputs are driven low. The LS610 and LS612 feature three-state map outputs, while the 'LS611 and 'LS613 feature open-collector map outputs. The corresponding pins of the 'LS612 and 'LS613 have no internal connections.

• Expands 4 address lines to 12 address lines
• Designed for paged memory mapping
• 'LS610 and 'LS611 provide output latches
• Selectable tri-state or open-collector mapped outputs
• Compatible with TMS9900 and other microprocessors