Infineon/CYPRESS CY7C1041BV33-25ZC

The CY7C1041BV33 is a high-performance CMOS static random access memory organized as 262,144 words × 16 bits. To write data to the device, drive Chip Enable (CE) and Write Enable (WE) inputs LOW. When Byte Low Enable (BLE) is LOW, data from the I/O pins (I/O₀–I/O₇) is written to the location specified by the address pins (A₀–A₁₇); when Byte High Enable (BHE) is LOW, data from the I/O pins (I/O₈–I/O₁₅) is written to the location specified by the address pins (A₀–A₁₇). To read data from the device, drive CE and Output Enable (OE) LOW while driving WE HIGH. When BLE is LOW, data from the addressed memory location appears on I/O₀–I/O₇; when BHE is LOW, the stored data appears on I/O₈–I/O₁₅. The input/output pins (I/O₀–I/O₁₅) are in a high-impedance state when the device is deselected (CE HIGH), the output is disabled (OE HIGH), both BHE and BLE are disabled (BHE and BLE HIGH), or during a write operation (CE LOW and WE LOW). The CY7C1041BV33 is available in a standard 44-pin, 400-mil wide-body SOJ package and a 44-pin TSOP II package, both featuring center power and ground pin configurations.

• High-speed
• Access time tₐₐ = 12 ns
• Low active power consumption
• 612 mW max
• Low CMOS standby power (commercial L version)
• 1.8 mW max
• 2.0V data retention (600 μW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion via CE and OE functions