Infineon/CYPRESS CY7C1049BN-15VC

The CY7C1049BN is a high-performance CMOS static random access memory organized as 524,288 words × 8 bits. Memory expansion is easily achieved through active-LOW chip enable (CE), active-LOW output enable (OE), and three-state drivers. To write data to the device, drive chip enable (CE) and write enable (WE) inputs LOW, then write data on the eight I/O pins (I/O₀ through I/O₇) to the location specified by the address pins (A₀ through A₁₈). To read data from the device, drive chip enable (CE) and output enable (OE) LOW while holding write enable (WE) HIGH; the contents of the memory location specified by the address pins will then appear on the I/O pins. The eight I/O pins (I/O₀ through I/O₇) are in a high-impedance state when the device is deselected (CE HIGH), the output is disabled (OE HIGH), or a write operation is in progress (CE LOW and WE LOW). The CY7C1049BN is offered in a standard 400-mil wide 36-pin SOJ package with center power and ground pin configuration.

• High speed
• tₐₐ = 12 ns
• Low active power
• 1320 mW (max)
• Low CMOS standby power (commercial L version)
• 2.75 mW (max)
• 2.0V data retention (400 μW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion via CE and OE functions