Infineon/CYPRESS CY8C4124PVA-442Z

PSoC 4 is a scalable and reconfigurable platform architecture for a family of mixed - signal programmable embedded system controllers with an ARM Cortex - M0 CPU, while being AEC - Q100 compliant. It combines programmable and re - configurable analog and digital blocks with flexible automatic routing. The PSoC 4100 product family, based on this platform, is a combination of a microcontroller with digital programmable logic, high - performance analog - to - digital conversion, opamp with Comparator mode, and standard communication and timing peripherals. The PSoC 4100 products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in - field tuning of the design. PSoC 4100 devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. The ARM Serial_Wire Debug (SWD) interface supports all programming and debug features of the device. Complete debug - on - chip functionality enables full device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The PSoC Creator Integrated Development Environment (IDE) provides fully integrated programming and debug support for PSoC 4100 devices. The SWD interface is fully compatible with industry standard third party tools. With the ability to disable debug features, with very robust flash protection, and by allowing customer - proprietary functionality to be implemented in on - chip programmable blocks, the PSoC 4100 family provides a level of security not possible with multi - chip application solutions or with microcontrollers.

• Automotive Electronics Council (AEC) AEC - Q100 qualified
• 24 MHz ARM Cortex - M0 CPU with single - cycle multiply
• Up to 32 kB of flash with Read Accelerator
• Up to 4 kB of SRAM
• One opamp with reconfigurable high - drive external and high - bandwidth internal drive, Comparator mode, and ADC input buffering capability
• 12 - bit, 806 Ksps SAR ADC with differential and single - ended modes and Channel Sequencer with signal averaging
• Two current DACs (IDACs) for general - purpose or capacitive sensing applications on any pin
• Two low - power comparators that operate in Deep Sleep
• 20 nA Stop Mode with GPIO pin wakeup
• Hibernate and Deep Sleep modes allow wakeup - time versus power trade - offs
• Cypress Capacitive Sigma - Delta (CSD) provides best - in - class SNR (>5;1) and water tolerance
• Cypress supplied software component makes capacitive sensing design easy
• Automatic hardware tuning (SmartSense™)
• LCD drive supported on all pins (common or segment)
• Operates in Deep Sleep mode with 4 bits per pin memory
• Two independent run - time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, UART, or LIN Slave 1.3, 2.1/2.2 functionality
• Four 16 - bit Timer/Counter Pulse - Width Modulator (TCPWM) blocks
• Center - aligned, Edge, and Pseudo - random modes
• Comparator - based triggering of Kill signals for motor drive and other high reliability digital logic applications
• 28 - pin SSOP package
• Any GPIO pin can be CapSense, LCD, analog, or digital
• Drive modes, strengths, and slew rates are programmable
• A Grade: - 40 ℃ to + 85 ℃
• S Grade: - 40 ℃ to + 105 ℃
• Integrated Development Environment provides schematic design entry and build (with analog and digital automatic routing)
• Applications Programming Interface (API Component) for all fixed - function and programmable peripherals
• After schematic entry, development can be done with ARM - based industry - standard development tools