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MXIC MX25L25673GZ4I-08G product image
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MXIC MX25L25673GZ4I-08G

Manufacturer
MXIC
MPN
MX25L25673GZ4I-08G
LCSC Part #
C2908108
Packaging
QFN-8
Customer #
Key Attributes
CMOS Serial Multi I/O Flash Memory
DatasheetMXIC MX25L25673GZ4I-08G
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement
In-Stock: 200
200 In stock, ships now
Minimum: 1Multiple: 1Sales Unit: Piece
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 7.1408$ 7.14
10+$ 6.1136$ 61.14
30+$ 5.4875$ 164.63
100+$ 4.9616$ 496.16
Standard Packaging480/Full Tray
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory
ManufacturerMXIC
PackagingQFN-8
Operating Temperature-40℃~+85℃
Features-
Memory Size256Mbit
Voltage - Supply2.7V~3.6V
Program / Erase Cycles100,000 cycles
Clock Frequency120MHz
Data Retention - TDR (Year)20 Years
Block Erase Time(tBE)-
Write Cycle Time(tWC)-
Page Programming Time (Tpp)750us
Standby Supply Current15uA
InterfaceSPI
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Features

AI Translation
  • Protocol Support - Single I/O, Dual I/O and Quad I/O
  • Supports DTR (Double Transfer Rate) Mode
  • Supports clock frequencies up to 133MHz
  • Quad I/O mode is permanently enabled
  • Supports Serial Peripheral Interface -- Mode 0 and Mode 3
  • Single Power Supply Operation - 2.7 to 3.6 volts for read, erase, and program operations
  • 268,435,456 x 1 bit structure or 134,217,728 x 2 bits (two I/O mode) structure or 67,108,864 x 4 bits (four I/O mode) structure
  • Latch-up protected to 100mA from -1V to Vcc +1V
  • Low Vcc write inhibit is from 1.5V to 2.5V
  • Fast read for SPI mode - Supports clock frequencies up to 133MHz for all protocols - Supports Fast Read, 2READ, DREAD, 4READ, QREAD instructions - Supports DTR (Double Transfer Rate) Mode - Configurable dummy cycle number for fast read operation
  • Default Quad I/O enable (QE bit '=1), and can not be changed
  • Supports Performance Enhance Mode - XIP (execute-in-place)
  • Quad Peripheral Interface (QPI) available
  • Equal 4K byte Sectors, or Equal Blocks with 32K byte or 64K byte each - Any Block can be erased individually
  • Programming: - 256byte page buffer - Quad Input/Output page program(4PP) to enhance program performance
  • Typical 100,000 erase/program cycles
  • 20 years data retention
  • Input Data Format: 1-byte Command code
  • Advanced Security Features: - Block lock protection. The BP0 - BP3 and T/B status bits define the size of the area to be protected against program and erase instructions - Individual sector protection function (Solid Protect)
  • Additional 4K bit secure OTP: - Features unique identifier - Factory locked identifiable, and customer lockable
  • Command Reset
  • Program/Erase Suspend and Resume operation