TI ADC34J25IRGZT

The ADC34J2x belongs to a family of high-linearity, ultra-low-power, dual-channel, 12-bit, 50MSPS to 160MSPS ADCs. These devices are specifically designed to support demanding high-input-frequency signals with wide dynamic range requirements. When the SYSREF input achieves whole-system synchronization, the clock input divider provides greater flexibility in system clock architecture design. The device supports a JESD204B interface, reducing the number of interface lines and enabling high system integration. The JESD204B interface is a serial interface that serializes the data output of each ADC through a single differential pair. An internal PLL multiplies the incoming ADC sampling clock by 20 to generate the bit clock used for serializing the 12-bit data from each channel. The device supports Subclass 1 with interface rates up to 3.2Gbps.

• Quad-channel
• 12-bit resolution
• 1.8V single supply
• Flexible input clock buffer supporting divide-by-1, divide-by-2, and divide-by-4
• SNR = 69.6dBFS, SFDR = 86dBc at f₁ₙ = 70MHz
• Ultra-low power: 203mW per channel at 160MSPS
• Channel isolation: 105dB
• Internal dither
• JESD204B serial interface: subclass 0, 1, 2 compatible, up to 3.2Gbps
• Supports one lane per ADC (up to 160MSPS)
• Multi-chip synchronization support
• Pin-compatible with 14-bit version devices
• Package: VQFN-48 (7mm x 7mm)

• Multi-carrier, multi-mode cellular base stations
• Radar and smart antenna arrays
• Motor control feedback
• Network and vector analyzers
• Communications test equipment
• Non-destructive testing
• Microwave receivers
• SDR quadrature and diversity radio receivers