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TI TMS320C6711DZDP200

Manufacturer
TI
MPN
TMS320C6711DZDP200
LCSC Part #
C2859964
Packaging
BGA-272
Customer #
Key Attributes
200MHz BGA-272 DSP (Digital Signal Processors) RoHS
DatasheetTI TMS320C6711DZDP200
RoHS Compliance2 documents available
In-Stock: 3
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QtyUnit PriceTotal Amount
1+$ 36.4817$ 36.48
40+$ 34.5458$ 1381.83
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/DSP (Digital Signal Processors)
ManufacturerTI
PackagingBGA-272
Operating Temperature0℃~+90℃
FeaturesHardware MAC acceleration;Parallel data channel;DMA data transfer;High-speed peripheral interface;RTC and timer
Clock Rate200MHz
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Introduction

AI Translation

Excellent-Price/Performance Floating-Point Digital Signal Processor (DSP): TMS320C6711D

Features

AI Translation
  • Eight 32-Bit Instructions/Cycle
  • 167-, 200-, 250-MHz Clock Rates
  • 6-, 5-, 4-ns Instruction Cycle Time
  • 1000, 1200, 1500 MFLOPS
  • Eight Highly Independent Functional Units: Four ALUs (Floating- and Fixed-Point), Two ALUs (Fixed-Point), Two Multipliers (Floating- and Fixed-Point)
  • Load-Store Architecture With 32 32-Bit General-Purpose Registers
  • Instruction Packing Reduces Code Size All Instructions Conditional
  • Hardware Support for IEEE Single-Precision and Double-Precision Instructions
  • Byte-Addressable (8-, 16-, 32-Bit Data)
  • 8-Bit Overflow Protection
  • Saturation
  • Bit-Field Extract, Set, Clear
  • Bit-Counting
  • Normalization
  • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
  • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
  • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Boot Mode: HPl, 8-, 16-, 32-Bit ROM Boot
  • Endianness: Little Endian, Big Endian
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 32-Bit External Memory Interface (EMIF): Glueless Interface to Asynchronous Memories: SRAM and EPROM, Glueless Interface to Synchronous Memories: SDRAM and SBSRAM, 256M-Byte Total Addressable External Memory Space
  • 16-Bit Host-Port Interface (HPI)
  • Two Multichannel Buffered Serial Ports (McBSPs): Direct Interface to T1/E1, MVIP, SCSA Framers, ST-Bus-Switching Compatible, Up to 256 Channels Each, AC97-Compatible
  • Serial-Peripheral-Interface (SPI) Compatible (Motorola)
  • Two 32-Bit General-Purpose Timers
  • Flexible Software Configurable PLL-Based Clock Generator Module
  • A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffixes)
  • CMos Technology: 0.13-μm/6 -Level Copper Metal Process
  • 3.3-V I/O, 1.4-V Internal (-250)
  • 3.3-V I/O, 1.20-V Internal