Infineon CY9AF156NAPMC-GE1
| Manufacturer | |
| MPN | CY9AF156NAPMC-GE1 |
| LCSC Part # | C20189746 |
| Packaging | LQFP-100(14x14) |
| Customer # | |
| Key Attributes | ARM Cortex-M3 32 Bit 40MHz LQFP-100(14x14) Microcontrollers RoHS |
| Datasheet | Infineon CY9AF156NAPMC-GE1 |
| RoHS Compliance | 1 documents available |
| Alternative Parts | 10 |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon | |
| Packaging | LQFP-100(14x14) | |
| Number of I/O | 83 | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.65V~3.6V | |
| EEPROM | - | |
| Program Storage Size | 544KB | |
| CPU Core | ARM Cortex-M3 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 40MHz | |
| Oscillator Type | Built-in |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon | |
| Packaging | LQFP-100(14x14) | |
| Number of I/O | 83 | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.65V~3.6V |
| Type | Description | |
|---|---|---|
| EEPROM | - | |
| Program Storage Size | 544KB | |
| CPU Core | ARM Cortex-M3 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 40MHz | |
| Oscillator Type | Built-in |
Help & FeedbackShow similar products (0) >
Introduction
AI Translation
The CY9A150RB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the Arm Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, and Communication Interfaces (UART, CSIO, I2C).
Features
AI Translation
- 32-bit Arm Cortex-M3 Core
- Processor version: r2p1
- Up to 40 MHz Frequency Operation
- Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels
- 24-bit System timer (Sys Tick): System timer for OS task management
- On-chip Memories
- [Flash memory]
- Dual operation Flash memory. Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously.
- Main area: Up to 512 Kbytes (Up to 496 Kbytes upper bank + 16 Kbytes lower bank)
- Work area: 32 Kbytes (lower bank)
- Read cycle: 0 wait-cycle
- Security function for code protection
- [SRAM]
- This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
- SRAM0: Up to 32 Kbytes
- SRAM1: Up to 32 Kbytes
- [Flash memory]
- External Bus Interface
- Supports SRAM, NOR NAND Flash memory device
- Up to 8 chip selects
- 8-/16-bit Data width
- Up to 25-bit Address bit
- Maximum area size: Up to 256 Mbytes
- Supports Address/Data multiplex
- Supports external RDY function
- Multi-function Serial Interface (Max 16 channels)
- 16 channels with 16 steps ×9-bit FIFO
- Operation mode is selectable from the followings for each channel: UART, CSIO, I2C
- [UART]
- Full-duplex double buffer
- Selection with or without parity supported
- Built-in dedicated baud rate generator
- External clock available as a serial clock
- Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4)
- Various error detection functions available (parity errors, framing errors, and overrun errors)
- [CSIO]
- Full-duplex double buffer
- Built-in dedicated baud rate generator
- Overrun error detection function available
- [I2C]
- Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
- DMA Controller (8 channels)
- 8 independently configured and operated channels
- Transfer can be started by software or request from the built-in peripherals
- Transfer address area: 32-bit (4 Gbytes)
- Transfer mode: Block transfer/Burst transfer/Demand transfer
- Transfer data type: byte/half-word/word
- Transfer block count: 1 to 16
- Number of transfers: 1 to 65536
- A/D Converter (Max 24 channels) [12-bit A/D Converter]
- Successive Approximation type
- Built-in 2 units
- Conversion time: 2.0 μs @ 2.7 V to 3.6 V
- Priority conversion available (priority at 2 levels)
- Scanning conversion mode
- Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps)
- Base Timer (Max 16 channels)
- Operation mode is selectable from the followings for each channel: 16-bit PWM timer, 16-bit PPG timer, 16-/32-bit reload timer, 16-/32-bit PWC timer
- General-Purpose I/O Port
- This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.
- Capable of pull-up control per pin
- Capable of reading pin level directly
- Built-in the port relocate function
- Up to 103 high-speed general-purpose I/O Ports @ 120 pin Package
- Some ports are 5 V tolerant I/O
- Dual Timer (32-/16-bit Down Counter)
- The Dual Timer consists of two programmable 32-/16-bit down counters.
- Operation mode is selectable from the followings for each channel: Free-running, Periodic (=Reload), One-shot
- Multi-function Timer
- The Multi-function timer is composed of the following blocks: 16-bit free-run timer × 3ch, Input capture × 4ch, Output compare × 6ch, A/D activation compare × 2ch, Waveform generator × 3ch, 16-bit PPG timer × 3ch.
- The following function can be used to achieve the motor control: PWM signal output function, DC chopper waveform output function, Dead time function, Input capture function, A/D convertor activate function, DTIF (Motor emergency stop) interrupt function
- Quadrature Position/Revolution Counter (QPRC)
- The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use as the up/down counter.
- The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
- 16-bit position counter
- 16-bit revolution counter
- Two 16-bit compare registers
- HDMI-CEC/Remote Control Reception (Up to 2 channels)
- HDMI-CEC transmission: Header block automatic transmission by judging Signal free
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 20.4438 | $ 20.44 |
| 200+ | $ 8.1578 | $ 1631.56 |
| 500+ | $ 7.8847 | $ 3942.35 |
| 900+ | $ 7.7505 | $ 6975.45 |
Standard Packaging900/Full Tray | ||
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon | |
| Packaging | LQFP-100(14x14) | |
| Number of I/O | 83 | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.65V~3.6V | |
| EEPROM | - | |
| Program Storage Size | 544KB | |
| CPU Core | ARM Cortex-M3 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 40MHz | |
| Oscillator Type | Built-in |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon | |
| Packaging | LQFP-100(14x14) | |
| Number of I/O | 83 | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.65V~3.6V |
| Type | Description | |
|---|---|---|
| EEPROM | - | |
| Program Storage Size | 544KB | |
| CPU Core | ARM Cortex-M3 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 40MHz | |
| Oscillator Type | Built-in |
Help & FeedbackShow similar products (0) >
Introduction
AI Translation
The CY9A150RB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the Arm Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, and Communication Interfaces (UART, CSIO, I2C).
Features
AI Translation
- 32-bit Arm Cortex-M3 Core
- Processor version: r2p1
- Up to 40 MHz Frequency Operation
- Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels
- 24-bit System timer (Sys Tick): System timer for OS task management
- On-chip Memories
- [Flash memory]
- Dual operation Flash memory. Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously.
- Main area: Up to 512 Kbytes (Up to 496 Kbytes upper bank + 16 Kbytes lower bank)
- Work area: 32 Kbytes (lower bank)
- Read cycle: 0 wait-cycle
- Security function for code protection
- [SRAM]
- This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
- SRAM0: Up to 32 Kbytes
- SRAM1: Up to 32 Kbytes
- [Flash memory]
- External Bus Interface
- Supports SRAM, NOR NAND Flash memory device
- Up to 8 chip selects
- 8-/16-bit Data width
- Up to 25-bit Address bit
- Maximum area size: Up to 256 Mbytes
- Supports Address/Data multiplex
- Supports external RDY function
- Multi-function Serial Interface (Max 16 channels)
- 16 channels with 16 steps ×9-bit FIFO
- Operation mode is selectable from the followings for each channel: UART, CSIO, I2C
- [UART]
- Full-duplex double buffer
- Selection with or without parity supported
- Built-in dedicated baud rate generator
- External clock available as a serial clock
- Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4)
- Various error detection functions available (parity errors, framing errors, and overrun errors)
- [CSIO]
- Full-duplex double buffer
- Built-in dedicated baud rate generator
- Overrun error detection function available
- [I2C]
- Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
- DMA Controller (8 channels)
- 8 independently configured and operated channels
- Transfer can be started by software or request from the built-in peripherals
- Transfer address area: 32-bit (4 Gbytes)
- Transfer mode: Block transfer/Burst transfer/Demand transfer
- Transfer data type: byte/half-word/word
- Transfer block count: 1 to 16
- Number of transfers: 1 to 65536
- A/D Converter (Max 24 channels) [12-bit A/D Converter]
- Successive Approximation type
- Built-in 2 units
- Conversion time: 2.0 μs @ 2.7 V to 3.6 V
- Priority conversion available (priority at 2 levels)
- Scanning conversion mode
- Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps)
- Base Timer (Max 16 channels)
- Operation mode is selectable from the followings for each channel: 16-bit PWM timer, 16-bit PPG timer, 16-/32-bit reload timer, 16-/32-bit PWC timer
- General-Purpose I/O Port
- This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.
- Capable of pull-up control per pin
- Capable of reading pin level directly
- Built-in the port relocate function
- Up to 103 high-speed general-purpose I/O Ports @ 120 pin Package
- Some ports are 5 V tolerant I/O
- Dual Timer (32-/16-bit Down Counter)
- The Dual Timer consists of two programmable 32-/16-bit down counters.
- Operation mode is selectable from the followings for each channel: Free-running, Periodic (=Reload), One-shot
- Multi-function Timer
- The Multi-function timer is composed of the following blocks: 16-bit free-run timer × 3ch, Input capture × 4ch, Output compare × 6ch, A/D activation compare × 2ch, Waveform generator × 3ch, 16-bit PPG timer × 3ch.
- The following function can be used to achieve the motor control: PWM signal output function, DC chopper waveform output function, Dead time function, Input capture function, A/D convertor activate function, DTIF (Motor emergency stop) interrupt function
- Quadrature Position/Revolution Counter (QPRC)
- The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use as the up/down counter.
- The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
- 16-bit position counter
- 16-bit revolution counter
- Two 16-bit compare registers
- HDMI-CEC/Remote Control Reception (Up to 2 channels)
- HDMI-CEC transmission: Header block automatic transmission by judging Signal free
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |
Alternative Parts
| MPN | Manufacturer | Packaging | Availability | Unit Price | ||
|---|---|---|---|---|---|---|
| CY9AF156NPMC-G-JNK1E2 | Infineon | LQFP-100(14x14) | 0 | $ 20.8064 | ||
| CY9AF156NPMC-G-JNN1E2 | Infineon | LQFP-100(14x14) | 0 | $ 20.4438 | ||
| CY9AF156NBPMC-G-JNE2 | Infineon/CYPRESS | LQFP-100(14x14) | 0 | $ 0.7839 | ||
| MB9AF156NBPMC-G-JNE2 | Infineon/CYPRESS | LQFP-100(14x14) | 0 | $ 0.3132 | ||
| CY9AF156NPMC-GE1 | Infineon | LQFP-100(14x14) | 0 | $ 20.8064 | ||
| CY9BF316NPMC-G-JNE1 | Infineon | LQFP-100(14x14) | 0 | $ 20.8064 | ||
| CY9BF316NPMC-G-JNE2 | Infineon/CYPRESS | LQFP-100(14x14) | 0 | $ 0.7839 | ||
| CY9BF116NPMC-G-JNE2 | Infineon/CYPRESS | LQFP-100(14x14) | 0 | $ 0.8826 | ||
| EFM32GG980F1024G-E-QFP100R | SILICON LABS | QFP-100(14x14) | 0 | $ 14.5903 | ||
| EFM32GG380F1024G-E-QFP100R | SILICON LABS | LQFP-100(14x14) | 0 | $ 5.6592 |

