Alliance Memory AS4C128M16D2-25BIN

The AS4C128M16D2 is an eight bank DDR DRAM organized as 8 banks x 16Mbit x 16. The AS4C128M16D2 achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency-1, (3) On Die Termination. All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O s are synchronized with a pair of bidirectional strobes (DQS, DQS) in a source synchronous fashion. Operating the eight memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.

• High speed data transfer rates with system frequency up to 400 MHz
• 8 internal banks for concurrent operation
• 4-bit prefetch architecture
• Programmable CAS Latency: 3, 4 ,5 , 6 and 7
• Programmable Additive Latency: 0, 1, 2, 3 , 4, 5 and 6
• Write Latency = Read Latency -1
• Programmable Wrap Sequence: Sequential or Interleave
• Programmable Burst Length: 4 and 8
• Automatic and Controlled Precharge Command
• Power Down Mode
• Auto Refresh and Self Refresh
• Refresh Interval: 7.8 μs (8192 cycles/64 ms) Tcase between 0 ℃ and 85 ℃
• ODT (On-Die Termination)
• Weak Strength Data-Output Driver Option
• Bidirectional differential Data Strobe (Single-ended data-strobe is an optional feature)
• On-Chip DLL aligns DQ and DQs transitions with CK transitions
• DQS can be disabled for single-ended data strobe
• Differential clock inputs CK and CK
• JEDEC Power Supply 1.8 V ± 0.1 V
• V 2DQ = 1.8 V ± 0.1 V
• Available in 84-ball FBGA
• RoHS compliant
• PASR Partial Array Self Refresh
• tRAS lockout supported