MICROCHIP ATSAM3N0BA-MU

The Atmel | SMART SAM3N series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex -M3 RISC processor. It operates at a maximum speed of 48 MHz and features up to 256 Kbytes of Flash and up to 24 Kbytes of SRAM. The peripheral set includes 2 USARTs, 2 UARTs, 2 TWIs, 3 SPIs, as well as a PWM timer, two 3-channel general-purpose 16-bit timers, an RTC, a 10-bit ADC, and a 10-bit DAC. The SAM3N devices have three software-selectable low-power modes: Sleep, Wait and Backup. In Sleep mode, the processor is stopped while all other functions can be kept running. In Wait mode, all clocks and functions are stopped but some peripherals can be configured to wake up the system based on predefined conditions. In Backup mode, only the RTC, RTT, 256-bit GPBR, and wake-up logic are running. The Real-time Event Managment allows peripherals to receive, react to and send events in Active and Sleep modes without processor intervention. The SAM3N series is ready for capacitive touch thanks to the Atmel QTouch library, offering an easy way to implement buttons, wheels and sliders. The SAM3N device is an entry-level general purpose microcontroller. That makes the SAM3N the ideal starting point to move from 8-/16-bit to 32-bit microcontrollers. It operates from 1.62V to 3.6V and is available in 48-pin, 64-pin and 100-pin QFP, 48-pin and 64-pin QFN, and 100-pin BGA packages. The SAM3N series is the ideal migration path from the SAM3S for applications that require a reduced BOM cost. The SAM3N series is pin-to-pin compatible with the SAM3S series. Its aggressive price point and high level of integration pushes its scope of use far into cost-sensitive, high-volume applications.

• Core
  • ARM Cortex-M3 revision 2.0 running at up to 48 MHz
  • Thumb-2 Instruction Set
  • 24-bit SysTick Counter
  • Nested Vector Interrupt Controller
  • Pin-to-pin compatible with SAM7S legacy products (48/64-pin versions) and SAM3S (48/64/100-pin versions)
  • Memories: From 16 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator, single plane; From 4 to 24 Kbytes embedded SRAM; 16 Kbytes ROM with embedded bootloader routines (UART) and IAP routines
  • Embedded voltage regulator for single supply operation
  • Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
  • Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure Detection and optional low power 32.768 kHz for RTC or device clock
  • High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for device startup. In-application trimming access for frequency adjustment
  • Slow Clock Internal RC oscillator as permanent low-power mode device clock
  • One PLL up to 130 MHz for device clock
  • Up to 10 Peripheral DMA (PDC) channels
• Low Power Modes: Sleep, Wait, and Backup modes, down to 1.2 μA in Backup mode with RTC, RTT, and 256-bit GPBR
• Peripherals
  • Up to 2 USARTs with RS-485 and SPI mode support. One USART (USART0) has ISO7816, IrDA and PDC support in addition
  • Two 2-wire UARTs
  • Two 2-wire Interfaces (I2C compatible)
  • One SPI
  • Up to two 3-channel 16-bit Timer Counters with capture, waveform, compare and PWM mode, Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor
  • 4-channel 16-bit PWM
  • 32-bit low-power Real-time Timer (RTT)
  • Low-power Real-time Clock (RTC) with calendar and alarm features
  • Up to 16 channels, 384 ksps 10-bit ADC
  • One 500 ksps 10-bit DAC
  • Register Write Protection
• I/O
  • Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and ondie Series Resistor Termination
  • Three 32-bit Parallel Input/Output Controllers