Intel/Altera EPF10K50EFI256-2

Altera's FLEX 10K devices are the industry's first embedded PLDs. Based on reconfigurable CMOS SRAM elements, the Flexible Logic Element MatriX (FLEX) architecture incorporates all the features necessary to implement common gate array macrofunctions. With up to 250,000 gates, FLEX 10K family devices provide sufficient density, speed, and features to integrate an entire system — including multiple 32-bit buses — into a single device. FLEX 10K devices are reconfigurable, allowing 100% testing prior to shipment. As a result, designers are not required to generate test vectors for fault coverage purposes. Furthermore, designers need not manage inventory across different ASIC designs; FLEX 10K devices can be configured on the board to implement the specific required functions.

• Industry's first embedded PLD family with on-chip SOPC integration
• Embedded array for implementing macrofunctions such as efficient memory and dedicated logic functions; logic array for general-purpose logic functions
• High density, with typical gate counts from 10,000 to 250,000 (see Tables 1 and 2)
• Up to 40,960 RAM bits; 2,048 bits per EAB, all usable without reducing logic capacity
• System-level features: MultiVolt™ I/O interface support; 5.0-V tolerant input pins on FLEX 10KA devices; low power consumption (typical standby current less than 0.5 mA for most devices); FLEX 10K and FLEX 10KA devices support PCI SIG PCI Local Bus Specification Revision 2.2; FLEX 10KA devices include pull-up clamp diodes selectable per pin for 3.3-V PCI compliance; select FLEX 10KA devices support 5.0-V PCI bus with loads of 8 or fewer; built-in IEEE Std. 1149.1-1990 JTAG BST circuitry consuming no device logic
• Devices manufactured on advanced process technology with 3.3-V or 5.0-V operating supply voltage (see Table 3)
• In-circuit reconfiguration (ICR) via external configuration device, intelligent controller, or JTAG port
• ClockLock™ and ClockBoost™ options for reduced clock delay/skew and clock multiplication
• Built-in low-skew clock distribution tree
• 100% functional testing of all devices, no test vectors or scan chains required
• Flexible interconnect: FastTrack® continuous routing structure for fast, predictable interconnect delays; dedicated carry chain for arithmetic functions such as fast adders, counters, and comparators (used automatically by software tools and macrofunctions); dedicated cascade chain for high-speed, high-fanin logic functions (used automatically by software tools and macrofunctions); tri-state emulation for internal tri-state buses; up to six global clock signals and four global clear signals
• Powerful I/O pins: individual tri-state output enable control per pin; open-drain option per I/O pin; programmable output slew-rate control to reduce switching noise; hot-socketing support on FLEX 10KA devices
• Peripheral registers for fast setup and clock-to-output delays
• Flexible packaging options: available in packages ranging from 84 to 600 pins (see Tables 4 and 5); pin-compatible with other FLEX 10K devices in the same package; FineLine BGA packages for maximum board space efficiency
• Altera development system provides software design support and automatic place-and-route for Windows-based PCs and Sun SPARCstation and HP 9000 Series 700/800 workstations
• Additional design entry and simulation support via EDIF 200 and 300 netlist files, LPM, DesignWare components, Verilog HDL, VHDL, and interfaces to popular EDA tools from Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic