Infineon/CYPRESS CY7C1049BNL-17VC

The CY7C1049BN is a high-performance CMOS static random access memory organized as 524,288 words × 8 bits. Memory expansion is easily achieved through an active-low chip enable (CE), an active-low output enable (OE), and three-state drivers. To write data to the device, CE and write enable (WE) are driven low, causing data present on the eight I/O pins (I/O₀–I/O₇) to be written to the location specified by the address pins (A₀–A₁₈). To read data from the device, CE and OE are driven low while WE is held high, causing the contents of the addressed memory cell to appear on the I/O pins. The eight I/O pins (I/O₀–I/O₇) are placed in a high-impedance state when the device is deselected (CE high), the outputs are disabled (OE high), or a write operation is in progress (CE low and WE low). The CY7C1049BN is offered in a standard 400-mil wide, 36-pin SOJ package with center power and ground pin configuration.

• High speed
• tₐₐ = 12 ns
• Low operating power
• 1320 mW (max)
• Low CMOS standby power (commercial L version)
• 2.75 mW (max)
• 2.0V data retention (400 μW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion via CE and OE functions