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TI SN74ALVCH162268GR

Manufacturer
MPN
SN74ALVCH162268GR
LCSC Part #
C2862080
Packaging
TSSOP-56-6.1mm
Customer #
Key Attributes
1.65V~3.6V 24mA 4.8ns TSSOP-56-6.1mm Universal Bus Functions RoHS
DatasheetTI SN74ALVCH162268GR
RoHS Compliance1 documents available
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Universal Bus Functions
ManufacturerTI
PackagingTSSOP-56-6.1mm
Operating Temperature-40℃~+85℃
Logic Family74ALVCH
Voltage - Supply1.65V~3.6V
Current - Output Low(IOL)24mA
Output TypeTri-State
Current - Output High(IOH)24mA
Setup Time3.4ns
Quiescent Current40uA
Propagation Delay4.8ns

Introduction

AI Translation

This is a 12-bit to 24-bit registered bus exchanger designed for 1.65V to 3.6V VCC operation. The SN74ALVCH162268 is intended for applications requiring data transfer from a narrow high-speed bus to a wide lower-frequency bus. The device provides synchronous data exchange between two ports. When the appropriate clock enable (CLKEN) input is low, data is stored into the internal registers on the low-to-high transition of the clock (CLK) input. The select (SEL) line is synchronous with CLK, selecting either 1B or 2B input data to be output to port A. For data transfer in the A-to-B direction, the A-to-1B path provides a two-stage pipeline, while the A-to-2B path is configured with a single storage register. Proper control of these inputs allows two consecutive 12-bit words to be synchronously presented on port B as a 24-bit word. Data flow is controlled by active-low output enables (OEA, OEB). These control inputs are registered, so bus direction changes are synchronous with CLK. The B outputs are designed to sink up to 12mA and incorporate equivalent 26Ω series resistors to reduce overshoot and undershoot. To ensure a high-impedance state during power-up or power-down, clock pulses should be applied as soon as possible, and OE should be connected to VCC through a pullup resistor; the minimum value of the resistor is determined by the sink current capability of the driver. Since OE is routed through the register, the active state of the outputs cannot be determined before the first clock pulse arrives. The active bus-hold circuit maintains unused or undriven inputs at a valid logic state. The use of pullup or pulldown resistors in conjunction with the bus-hold circuit is not recommended.

Features

AI Translation
  • Member of Texas Instruments Widebus™ family
  • Operating voltage range: 1.65V to 3.6V
  • Maximum propagation delay tpd of 4.8ns at 3.3V
  • Output drive capability of ±24mA at 3.3V
  • Port B outputs feature integrated equivalent 26Ω series resistors, eliminating external resistors
  • Data inputs with bus-hold, no external pull-up/pull-down resistors required
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD protection exceeds JESD 22
  • 2000V Human Body Model (A114-A) ESD protection
  • 200V Machine Model (A115-A) ESD protection