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Wuxi I-core Elec AIP74ALVC164245TA48.TR

Manufacturer
Wuxi I-core ElecAsian Brands
MPN
AIP74ALVC164245TA48.TR
LCSC Part #
C6798233
Packaging
TSSOP-48-6.1mm
Customer #
Key Attributes
16-bit Dual Supply Translating Transceiver; 3-state
DatasheetWuxi I-core Elec AIP74ALVC164245TA48.TR
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters
ManufacturerWuxi I-core Elec
PackagingTSSOP-48-6.1mm
output typeTri-State
Input Type-
Logic Family74ALVC
Voltage - Supply-
Propagation Delay5.8ns@3.3V,50pF
Output Logic Level - Low550mV
FeaturesControllable output enable;Overvoltage-tolerant input
Operating Temperature-40℃~+105℃
Input Logic Level - Low700mV;800mV
Input Logic Level - High1.7V;2V
Output Logic Level - High-
Quiescent Current(Iq)40uA
Number of Channels-;2
Current - Output High(IOH)24mA
Current - Output Low(IOL)24mA

Introduction

AI Translation

The AiP74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The AiP74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3V and 5V bus in a mixed 3V and 5V supply environment. This device can be used as two 8-bit transceivers or one 16-bit transceiver. The direction control inputs (1DIR and 2DIR) determine the direction of the data flow. nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables data from nBn ports to nAn ports. The output enable inputs (1 OE(overline) and 2 OE), when HIGH, disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins nAn, n OE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B). In suspend mode, when one of the supply voltages is zero, there will be no current flow from the non-zero supply towards the zero supply. The nAn-outputs must be set 3-state and the voltage on the A-bus must be smaller than Vdiode (typical 0.7V). VCC(B) ≥ VCC(A) (except in suspend mode).

Features

AI Translation
  • 5V tolerant inputs/outputs for interfacing with 5V log
  • Wide supply voltage range: 3V port (VCC(A)): 1.5V to 3.6V 5V port (VCC(B)): 1.2V to 5.5V
  • CMOS low power consumption
  • Direct interface with TTL levels
  • Control inputs voltage range from 2.7V to 5.5V
  • Inputs accept voltages up to 5.5V
  • High-impedance outputs when VCC(A) or VCC(B) = 0V
  • Specified from -40°C to +105°C Packaging information: TSSOP48