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Modelos EDAEasyEDA
MICROCHIP PIC24FJ128GB202-E/SP
| Fabricante | |
| N.º de pieza fab. | PIC24FJ128GB202-E/SP |
| Nº LCSC | C643607 |
| Emb. | SPDIP-28 |
| Número de Cliente | |
| Atrib. clave | PIC 16 Bit 32MHz SPDIP-28 Microcontrollers RoHS |
| Hoja de Datos | MICROCHIP PIC24FJ128GB202-E/SP |
| Cumplimiento RoHS | 2 documentos disponibles |
| Piezas alternativas | 1 |
Especificaciones del Producto
Todo
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Fabricante | MICROCHIP | |
| Emb. | SPDIP-28 | |
| ADC (Bit) | 10bit;12bit | |
| Number of I/O | 20 | |
| Operating Temperature | -40℃~+125℃ | |
| Voltage - Supply | 2V~3.6V | |
| Program Memory Type | FLASH | |
| EEPROM | - | |
| Program Storage Size | 128KB | |
| CPU Core | PIC | |
| Core Size | 16 Bit | |
| CPU Maximum Speed | 32MHz | |
| Oscillator Type | Built-in |
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Fabricante | MICROCHIP | |
| Emb. | SPDIP-28 | |
| ADC (Bit) | 10bit;12bit | |
| Number of I/O | 20 | |
| Operating Temperature | -40℃~+125℃ | |
| Voltage - Supply | 2V~3.6V |
| Tipo | Descripción | |
|---|---|---|
| Program Memory Type | FLASH | |
| EEPROM | - | |
| Program Storage Size | 128KB | |
| CPU Core | PIC | |
| Core Size | 16 Bit | |
| CPU Maximum Speed | 32MHz | |
| Oscillator Type | Built-in |
Ayuda y comentariosMostrar productos similares (0) >
Características
Traducción por IA
- AES Engine with 128,192 or 256 - Bit Key
- Supports ECB, CBC, OFB, CTR and CFB128 modes
- DES/Triple DES (TDES) Engine: Supports 2 - Key and 3 - Key EDE or DED TDES
- Supports up to Three Unique Keys for TDES
- Programmatically Secure
- True Random Number Generator
- Pseudorandom Number Generator
- Non - Readable, On - Chip, OTP Key Storages
- USB ×2.0 On - The - Go (OTG) Compliant
- Dual Role Capable; can Act as Either Host or Peripheral
- Low - Speed (1.5 Mb/s) and Full - Speed (12 Mb/s) USB Operation in Host mode
- Full - Speed USB Operation in Device mode
- High - Precision PLL for USB
- USB Device mode Operation from FRC Oscillator: No crystal oscillator required
- Supports up to 32 Endpoints (16 bidirectional): USB module can use any RAM locations on the device as USB endpoint buffers
- On - Chip USB Transceiver
- Supports Control, Interrupt, Isochronous and Bulk Transfers
- On - Chip Pull - up and Pull - down Resistors
- Multiple Power Management Options for Extreme Power Reduction:
- VBAT allows the device to transition to a backup battery for the lowest power consumption with RTCC
- Deep Sleep allows near total power - down, with the ability to wake - up on internal or external triggers
- Sleep and Idle modes selectively shut down peripherals and/or core for substantial power reduction and fast wake - up
- Doze mode allows CPU to run at a lower clock speed than peripherals
- Alternate Clock modes allow On - the - Fly Switching to a Lower Clock Speed for Selective Power Reduction
- Extreme Low - Power Current Consumption for Deep Sleep:
- WDT: 270 nA @3.3V typical
- RTCC: 400 nA @ 32 kHz, 3.3V typical
- Deep Sleep current: 40 nA, 3.3V typical
- 10/12 - Bit, 12 - Channel Analog - to - Digital (A/D) Converter:
- Conversion rate of 500 ksps (10 - bit), 200 ksps (12 - bit)
- Conversion available during Sleep and Idle
- Three Rail - to - Rail, Enhanced Analog Comparators with Programmable Input/Output Configuration
- Three On - Chip Programmable Voltage References
- Charge Time Measurement Unit (CTMU):
- Used for capacitive touch sensing, up to 12 channels
- Time measurement down to 100 ps resolution
- Operation in Sleep mode
- Up to Five External Interrupt Sources
- Peripheral Pin Select (PPS); Allows Independent I/O Mapping of many Peripherals
- Five 16 - Bit Timers/Counters with Prescaler: Can be paired as 32 - bit timers/counters
- Six - Channel DMA supports All Peripheral modules: Minimizes CPU overhead and increases data throughput
- Six Input Capture modules, each with a Dedicated 16 - Bit Timer
- Six Output Compare/PWM modules, each with a Dedicated 16 - Bit Timer
- Enhanced Parallel Master/Slave Port (EPMP/EPSP)
- Hardware Real - Time Clock/Calendar (RTCC): Runs in Sleep, Deep Sleep and VBAT modes
- Three 3 - Wire/4 - Wire SPI modules:
- Support four Frame modes
- Variable FIFO buffer
- Π|2s mode
- Variable width from 2 - bit to 32 - bit
- Two |²C™ modules Support Multi - Master/Slave mode and 7 - Bit/10 - Bit Addressing
- Four UART modules:
- Support RS - 485, RS - 232 and LIN/J2602
- On - chip hardware encoder/decoder for IrDA
- Smart Card ISO 7816 support on UART1 and UART2 only:
- T = 0 protocol with automatic error handling
- T = 1 protocol
- Dedicated Guard Time Counter (GTC)
- Dedicated Waiting Time Counter (WTC)
- Auto - wake - up on Auto - Baud Detect (ABD)
- 4 - level deep FIFO buffer
- Programmable 32 - Bit Cyclic Redundancy Check (CRC) Generator
- Digital Signal Modulator provides On - Chip FSK and PSK Modulation for a Digital Signal Stream
- High - Current Sink/Source (18 mA/18 mA) on All I/O Pins
- Configurable Open - Drain Outputs on Digital I/O Pins
- 5.5V Tolerant Inputs on Most Pins
- Modified Harvard Architecture
- Up to 16 MIPS Operation @32 MHz
- 8 MHz Internal Oscillator:
- 96 MHz PLL option
- Multiple clock divide options
- Run - time self - calibration capability for maintaining better than ±0.20% accuracy
- Fast start - up
- 17 - Bit × 7 - Bit Single - Cycle Hardware Fractional/Integer Multiplier
- 32 - Bit by 16 - Bit Hardware Divider
- 16×16 - Bit Working Register Array
- C Compiler Optimized Instruction Set Architecture (ISA)
- Two Address Generation Units (AGUs) for Separate Read and Write Addressing of Data Memory
- Supply Voltage Range of 2.0V to 3.6V
- Two On - Chip Voltage Regulators (1.8V and 1.2V) for Regular and Extreme Low - Power Operation
- 20,000 Erase/Write Cycle Endurance Flash Program Memory, Typical
- Flash Data Retention: 20 Years Minimum
- Self - Programmable under Software Control
- Programmable Reference Clock Output
- In - Circuit Serial Programming™ (ICSP™) and In - Circuit Emulation (ICE) via 2 Pins
- JTAG Programming and Boundary Scan Support
- Fail - Safe Clock Monitor (FSCM) Operation: Detects clock failure and switches to on - chip, Low - Power RC Oscillator
- Power - on Reset (POR), Power - up Timer (PWRT) and Oscillator Start - up Timer (OST)
- Separate Brown - out Reset (BOR) and Deep Sleep Brown - out Reset (DSBOR) Circuits
- Programmable High/Low - Voltage Detect (HLVD)
- Flexible Watchdog Timer (WDT) with its Own RC Oscillator for Reliable Operation
- Standard and Ultra Low - Power Watchdog Timers (ULPW) for Reliable Operation in Standard and Deep Sleep modes
Agotado
Avisarme
Mínimo: 1Múltiplo: 1Unidad de venta: Piece
Añadir a la Lista BOM
| Cant. | Prec. unit.(Solo como referencia) | Importo total |
|---|---|---|
| 1+ | $ 5.7201 | $ 5.72 |
| 200+ | $ 2.2134 | $ 442.68 |
| 500+ | $ 2.1362 | $ 1068.10 |
| 1,000+ | $ 2.0976 | $ 2097.60 |
Encapsulado Estándar15/Full Tube | ||
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Especificaciones del Producto
Todo
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Fabricante | MICROCHIP | |
| Emb. | SPDIP-28 | |
| ADC (Bit) | 10bit;12bit | |
| Number of I/O | 20 | |
| Operating Temperature | -40℃~+125℃ | |
| Voltage - Supply | 2V~3.6V | |
| Program Memory Type | FLASH | |
| EEPROM | - | |
| Program Storage Size | 128KB | |
| CPU Core | PIC | |
| Core Size | 16 Bit | |
| CPU Maximum Speed | 32MHz | |
| Oscillator Type | Built-in |
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Fabricante | MICROCHIP | |
| Emb. | SPDIP-28 | |
| ADC (Bit) | 10bit;12bit | |
| Number of I/O | 20 | |
| Operating Temperature | -40℃~+125℃ | |
| Voltage - Supply | 2V~3.6V |
| Tipo | Descripción | |
|---|---|---|
| Program Memory Type | FLASH | |
| EEPROM | - | |
| Program Storage Size | 128KB | |
| CPU Core | PIC | |
| Core Size | 16 Bit | |
| CPU Maximum Speed | 32MHz | |
| Oscillator Type | Built-in |
Ayuda y comentariosMostrar productos similares (0) >
Características
Traducción por IA
- AES Engine with 128,192 or 256 - Bit Key
- Supports ECB, CBC, OFB, CTR and CFB128 modes
- DES/Triple DES (TDES) Engine: Supports 2 - Key and 3 - Key EDE or DED TDES
- Supports up to Three Unique Keys for TDES
- Programmatically Secure
- True Random Number Generator
- Pseudorandom Number Generator
- Non - Readable, On - Chip, OTP Key Storages
- USB ×2.0 On - The - Go (OTG) Compliant
- Dual Role Capable; can Act as Either Host or Peripheral
- Low - Speed (1.5 Mb/s) and Full - Speed (12 Mb/s) USB Operation in Host mode
- Full - Speed USB Operation in Device mode
- High - Precision PLL for USB
- USB Device mode Operation from FRC Oscillator: No crystal oscillator required
- Supports up to 32 Endpoints (16 bidirectional): USB module can use any RAM locations on the device as USB endpoint buffers
- On - Chip USB Transceiver
- Supports Control, Interrupt, Isochronous and Bulk Transfers
- On - Chip Pull - up and Pull - down Resistors
- Multiple Power Management Options for Extreme Power Reduction:
- VBAT allows the device to transition to a backup battery for the lowest power consumption with RTCC
- Deep Sleep allows near total power - down, with the ability to wake - up on internal or external triggers
- Sleep and Idle modes selectively shut down peripherals and/or core for substantial power reduction and fast wake - up
- Doze mode allows CPU to run at a lower clock speed than peripherals
- Alternate Clock modes allow On - the - Fly Switching to a Lower Clock Speed for Selective Power Reduction
- Extreme Low - Power Current Consumption for Deep Sleep:
- WDT: 270 nA @3.3V typical
- RTCC: 400 nA @ 32 kHz, 3.3V typical
- Deep Sleep current: 40 nA, 3.3V typical
- 10/12 - Bit, 12 - Channel Analog - to - Digital (A/D) Converter:
- Conversion rate of 500 ksps (10 - bit), 200 ksps (12 - bit)
- Conversion available during Sleep and Idle
- Three Rail - to - Rail, Enhanced Analog Comparators with Programmable Input/Output Configuration
- Three On - Chip Programmable Voltage References
- Charge Time Measurement Unit (CTMU):
- Used for capacitive touch sensing, up to 12 channels
- Time measurement down to 100 ps resolution
- Operation in Sleep mode
- Up to Five External Interrupt Sources
- Peripheral Pin Select (PPS); Allows Independent I/O Mapping of many Peripherals
- Five 16 - Bit Timers/Counters with Prescaler: Can be paired as 32 - bit timers/counters
- Six - Channel DMA supports All Peripheral modules: Minimizes CPU overhead and increases data throughput
- Six Input Capture modules, each with a Dedicated 16 - Bit Timer
- Six Output Compare/PWM modules, each with a Dedicated 16 - Bit Timer
- Enhanced Parallel Master/Slave Port (EPMP/EPSP)
- Hardware Real - Time Clock/Calendar (RTCC): Runs in Sleep, Deep Sleep and VBAT modes
- Three 3 - Wire/4 - Wire SPI modules:
- Support four Frame modes
- Variable FIFO buffer
- Π|2s mode
- Variable width from 2 - bit to 32 - bit
- Two |²C™ modules Support Multi - Master/Slave mode and 7 - Bit/10 - Bit Addressing
- Four UART modules:
- Support RS - 485, RS - 232 and LIN/J2602
- On - chip hardware encoder/decoder for IrDA
- Smart Card ISO 7816 support on UART1 and UART2 only:
- T = 0 protocol with automatic error handling
- T = 1 protocol
- Dedicated Guard Time Counter (GTC)
- Dedicated Waiting Time Counter (WTC)
- Auto - wake - up on Auto - Baud Detect (ABD)
- 4 - level deep FIFO buffer
- Programmable 32 - Bit Cyclic Redundancy Check (CRC) Generator
- Digital Signal Modulator provides On - Chip FSK and PSK Modulation for a Digital Signal Stream
- High - Current Sink/Source (18 mA/18 mA) on All I/O Pins
- Configurable Open - Drain Outputs on Digital I/O Pins
- 5.5V Tolerant Inputs on Most Pins
- Modified Harvard Architecture
- Up to 16 MIPS Operation @32 MHz
- 8 MHz Internal Oscillator:
- 96 MHz PLL option
- Multiple clock divide options
- Run - time self - calibration capability for maintaining better than ±0.20% accuracy
- Fast start - up
- 17 - Bit × 7 - Bit Single - Cycle Hardware Fractional/Integer Multiplier
- 32 - Bit by 16 - Bit Hardware Divider
- 16×16 - Bit Working Register Array
- C Compiler Optimized Instruction Set Architecture (ISA)
- Two Address Generation Units (AGUs) for Separate Read and Write Addressing of Data Memory
- Supply Voltage Range of 2.0V to 3.6V
- Two On - Chip Voltage Regulators (1.8V and 1.2V) for Regular and Extreme Low - Power Operation
- 20,000 Erase/Write Cycle Endurance Flash Program Memory, Typical
- Flash Data Retention: 20 Years Minimum
- Self - Programmable under Software Control
- Programmable Reference Clock Output
- In - Circuit Serial Programming™ (ICSP™) and In - Circuit Emulation (ICE) via 2 Pins
- JTAG Programming and Boundary Scan Support
- Fail - Safe Clock Monitor (FSCM) Operation: Detects clock failure and switches to on - chip, Low - Power RC Oscillator
- Power - on Reset (POR), Power - up Timer (PWRT) and Oscillator Start - up Timer (OST)
- Separate Brown - out Reset (BOR) and Deep Sleep Brown - out Reset (DSBOR) Circuits
- Programmable High/Low - Voltage Detect (HLVD)
- Flexible Watchdog Timer (WDT) with its Own RC Oscillator for Reliable Operation
- Standard and Ultra Low - Power Watchdog Timers (ULPW) for Reliable Operation in Standard and Deep Sleep modes
C643607 Biblioteca EasyEDA
Cumplimiento & Códigos de Exportación
| Tipo | Detalles |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 5A992C |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Tipo | Detalles |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 5A992C |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Tipo | Detalles |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |
Piezas alternativas
| MPN | Fabricante | Empaque | Disponibilidad | Precio unitario | ||
|---|---|---|---|---|---|---|
| PIC24FJ128GB202-I/SP | MICROCHIP | SPDIP-28 | 20 | $ 13.1424 |