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Infineon CY91F526LSEPMC-GSE2 product image
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Infineon CY91F526LSEPMC-GSE2

Manufacturer
Infineon
MPN
CY91F526LSEPMC-GSE2
LCSC Part #
C7156348
Packaging
LQFP-176(24x24)
Customer #
Key Attributes
FR81S 32 Bit 80MHz LQFP-176(24x24) Microcontrollers RoHS
DatasheetInfineon CY91F526LSEPMC-GSE2
Alternative Parts1
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QtyUnit Price(Reference Only)Total Amount
1+$ 63.3364$ 63.34
200+$ 25.2724$ 5054.48
400+$ 24.4279$ 9771.16
800+$ 24.0105$ 19208.40
Standard Packaging400/Full Tray
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microcontrollers
ManufacturerInfineon
PackagingLQFP-176(24x24)
DAC (Bit)8bit
ADC (Bit)12bit
Number of I/O152
Operating Temperature-40℃~+105℃
Program Memory TypeFLASH
Voltage - Supply2.7V~5.5V
EEPROM64KB
Program Storage Size1.0625MB
CPU CoreFR81S
Core Size32 Bit
CPU Maximum Speed80MHz
Oscillator TypeExternal
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Features

AI Translation
  • 32-bit RISC architecture with load/store structure and 5-stage pipeline
  • Maximum operating frequency: 80 MHz (source oscillation = 4.0 MHz, 20x multiplier (PLL clock multiplication system))
  • General-purpose registers: 32-bit × 16 banks
  • 16-bit fixed-length instructions (basic instructions), 1 instruction per cycle
  • Instruction set for embedded applications, including memory-to-memory transfer, bit manipulation, barrel shift instructions, etc.
  • High-level language instruction support
  • Function entry/exit instructions
  • Multiple load and store instructions for register contents
  • Bit search instructions supporting logic-1 detection, 0 detection, and change-point detection
  • Branch instructions with delay slots
  • Reduced branch processing overhead
  • Register interlock function
  • Facilitates assembly language programming
  • Built-in multiplier with instruction-level support
  • Signed 32-bit multiplication: 5 cycles
  • Signed 16-bit multiplication: 3 cycles
  • Interrupt (PC/PS save): 6 cycles (16 priority levels)
  • Harvard architecture supporting simultaneous program and data access
  • Compatible with FR series instructions
  • Built-in MPU with 8 configurable shared protection regions for instructions and data, controlling access rights in privileged and user modes
  • Built-in FPU compliant with IEEE 754, floating-point registers: 32-bit × 16 banks
  • Clock generation (with SSCG), supporting main oscillation (4 MHz ~ 16 MHz), sub oscillation (32 kHz) or no sub oscillation, PLL multiplication ratio: 1 ~ 20x, built-in 100 kHz CR oscillator
  • Built-in program flash: CY91F522: 256 + 64 KB, CY91F523: 384 + 64 KB, CY91F524: 512 + 64 KB, CY91F525: 768 + 64 KB, CY91F526: 1024 + 64 KB
  • Built-in data flash (WorkFlash): 64 KB
  • Built-in RAM: main RAM (CY91F522: 48 KB, CY91F523: 48 KB, CY91F524: 64 KB, CY91F525: 96 KB, CY91F526: 128 KB), backup RAM 8 KB
  • GPIO count varies by model and sub oscillation configuration: 44/42, 56/54, 76/74, 96/94, 120/118, 152/150, including 16 I2C open-drain ports
  • External bus interface: 22-bit address, 16-bit data
  • DMA controller: up to 16 simultaneous channels, 2 transfer trigger sources (internal peripheral request and software)
  • Successive approximation ADC: 12-bit resolution, up to 48 channels (32 + 16), conversion time: 1.4 μs
  • R-2R DAC: 8-bit resolution, 2 channels
  • External interrupt inputs: 8 channels × 2 units, 16 channels total, supporting level ("H"/"L") or edge (rising or falling) detection
  • Multi-function serial communication (built-in TX/RX FIFO): up to 12 channels, of which 4 channels (ch.6, ch.8, ch.9, ch.11) support 5 V tolerant input and CMOS hysteresis input
  • UART: full-duplex double-buffer system, 64-stage TX FIFO, 64-stage RX FIFO, selectable parity or no parity, dedicated built-in baud rate generator, external clock usable as transfer clock, parity/frame/overrun error detection, DMA transfer support
  • CSIO: full-duplex double-buffer system, 64-stage TX FIFO, 64-stage RX FIFO, SPI support; master/slave mode; configurable data length of 5 ~ 16, 20, 24, 32 bits; dedicated built-in baud rate generator (master mode); external clock input (slave mode); overrun error detection; DMA transfer support; serial chip select SPI function
  • Asynchronous serial interface for LIN: full-duplex double-buffer system, 64-stage TX FIFO, 64-stage RX FIFO; LIN protocol revision 2.1 support; master/slave mode; frame and overrun error detection; LIN sync break generation and detection; LIN sync delimiter generation; dedicated built-in baud rate generator; external clock adjustment via reload counter; DMA transfer support; hardware assist function
  • I2C interface: 2 channels (ch.3, ch.4) supporting standard/fast mode; 6 channels (ch.5 ~ ch.8, ch.10, ch.11) supporting standard mode; full-duplex double-buffer system, 64-stage TX FIFO, 64-stage RX FIFO

Applications

AI Translation
  • Automotive body control
  • Industrial control
  • Consumer electronics
  • Medical devices
  • Test & measurement

Alternative Parts

MPNManufacturerAlternative TypePackagingAvailabilityUnit Price
CY91F526LSBPMC-GSE1Infineon/CYPRESSSimilarLQFP-176(24x24)0$ 2.0075
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