Infineon CY8C614ABZI-S2F44T

PSoC 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for IoT applications. The CY8C61x8/A product family, based on the PSoC 6 MCU platform, is a combination of a dual CPU microcontroller with low-power flash technology, digital programmable logic, high-performance analog-to-digital and standard communication and timing peripherals.

• 150-MHz Arm Cortex-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU)
• 100-MHz Cortex-M0+ CPU with single-cycle multiply and MPU
• User-selectable core logic operation at either 1.1V or 0.9V
• Active CPU current slope with 1.1-V core operation: Cortex-M4: 40 µA/MHz; Cortex-M0+: 28 µA/MHz
• Active CPU current slope with 0.9-V core operation: Cortex-M4: 27 µA/MHz; Cortex-M0+: 20 µA/MHz
• Three DMA controllers
• 2048-KB application flash, 32-KB auxiliary flash (AUXflash), and 32-KB supervisory flash (Sflash); read-while-write (RWW) support. Two 8-KB flash caches, one for each CPU.
• 1024-KB SRAM with three independent blocks for power and data retention control
• One-time-programmable (OTP) 1-Kb eFuse array
• Six power modes for fine-grained power management
• Deep Sleep mode current of 7 µA with 64-KB SRAM retention
• On-chip DC-DC buck converter, < 1 µA quiescent current
• Backup domain with 64 bytes of memory and real-time clock
• 8-MHz internal main oscillator (IMO) with ±2% accuracy
• Ultra-low-power 32-kHz internal low-speed oscillator (ILO)
• On-chip crystal oscillators (16 to 35 MHz, and 32 kHz)
• Two phase-locked loops (PLLs) for multiplying clock frequencies
• Frequency-locked loop (FLL) for multiplying IMO frequency
• Integer and fractional peripheral clock dividers
• Execute-In-Place (XIP) from external quad SPI flash
• On-the-fly encryption and decryption
• 4-KB cache for greater XIP performance with lower power
• Supports single, dual, quad, dual-quad, and octal interfaces with throughput up to 640 Mbps
• Supports up to 101 segments and up to 8 commons
• 13 run-time configurable serial communication blocks (SCBs): Eight SCBs: configurable as SPI, I2C, or UART; Four SCBs: configurable as I2C or UART; One Deep Sleep SCB: configurable as SPI or I2C
• USB Full-Speed device interface
• Two independent SD Host Controller/eMMC/SD controllers
• Two pulse density modulation (PDM) channels and two I2S channels with time division multiplexed (TDM) mode
• Thirty-two timer/counter/pulse-width modulators (TCPWMs)
• Center-aligned, edge, and pseudo-random modes
• Comparator-based triggering of kill signals
• 12-bit 2-Msps SAR ADC with differential and single-ended modes and 16-channel sequencer with result averaging
• Two low-power comparators available in system Deep Sleep and Hibernate modes
• Built-in temperature sensor connected to ADC
• Two Smart I/O ports (16 I/Os) enable Boolean operations on GPIO pins; available during system Deep Sleep
• Programmable drive modes, strengths, and slew rates
• Six overvoltage-tolerant (OVT) pins
• Cypress CapSense sigma-delta (CSD) provides best-in-class signal-to-noise ratio (SNR), liquid tolerance, and proximity sensing
• Enables dynamic usage of both self and mutual sensing
• Automatic hardware tuning (SmartSense)
• Authentication during boot using hardware hashing
• All debug and test ingress paths can be disabled
• Up to eight protection contexts
• Hardware acceleration for symmetric and asymmetric cryptographic methods and hash functions
• True random number generator (TRNG) function
• Eight counters provide event or duration monitoring of on-chip resources