GSI Technology GS8342Q18BGD-250I

GS8342Q08/09/18/36BD conforms to the SigmaQuad-II SRAM pin-out standard for separate I/O synchronous SRAM. These are 37,748,736-bit (36Mb) SRAMs, part of a low-power, low-voltage HSTL I/O SRAM family designed to operate at the speeds required to achieve cost-effective, high-performance networking systems. SigmaQuad-II SRAMs are synchronous devices that employ two input register clock inputs, K and K̄, and also allow users to control the output register clock inputs quasi-independently via the C and C̄ clock inputs. The internal read/write operations of SigmaQuad-II B2 RAM are twice as wide as the device I/O bus, with data handled through an input data bus demultiplexer and an output data multiplexer. Separate I/O SRAMs are attractive in applications requiring alternating read and write operations, with their interface and truth table optimized for alternating reads and writes, but are less suited for applications requiring multiple consecutive reads or writes.

• Simultaneous read/write SigmaQuad interface
• JEDEC standard pin-out and package
• Double data rate interface
• Byte write control sampled at data input
• Burst length of 2 read and write
• 1.8 V +100/-100 mV core supply
• 1.5 V or 1.8 V HSTL interface
• Pipelined read operation
• Fully coherent read/write pipeline
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG boundary scan compliant
• Pin-compatible with existing 144 Mb devices
• 165-ball, 13 mm × 15 mm, 1 mm ball pitch BGA package
• RoHS-compliant 165-ball BGA package available

• High-performance network systems