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Alliance Memory AS4C128M16D3LB-12BIN
| Manufacturer | |
| MPN | AS4C128M16D3LB-12BIN |
| LCSC Part # | C570201 |
| Packaging | FBGA-96(8x13) |
| Customer # | |
| Key Attributes | 2Gbit 1.283V~1.45V 800MHz DDR3L SDRAM FBGA-96(8x13) Memory |
| Datasheet | Alliance Memory AS4C128M16D3LB-12BIN |
| Alternative Parts | 1 |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | Alliance Memory | |
| Packaging | FBGA-96(8x13) | |
| Operating Temperature | -40℃~+95℃ | |
| Features | Auto precharge function;Data mask function;Dynamic on-chip termination;ZQ calibration function;Asynchronous reset function | |
| Refresh Current | - | |
| Memory Size | 2Gbit | |
| Voltage - Supply | 1.283V~1.45V | |
| Clock Frequency | 800MHz | |
| Memory Format | DDR3L SDRAM | |
| Current - Supply | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | Alliance Memory | |
| Packaging | FBGA-96(8x13) | |
| Operating Temperature | -40℃~+95℃ | |
| Features | Auto precharge function;Data mask function;Dynamic on-chip termination;ZQ calibration function;Asynchronous reset function | |
| Refresh Current | - |
| Type | Description | |
|---|---|---|
| Memory Size | 2Gbit | |
| Voltage - Supply | 1.283V~1.45V | |
| Clock Frequency | 800MHz | |
| Memory Format | DDR3L SDRAM | |
| Current - Supply | - |
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Features
AI Translation
- Double-data-rate architecture; two data transfers per clock cycle
- The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
- Bi-directional differential data strobe (DQS and DQS) is transmitted/ received with data for capturing data at the receiver
- DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
- Differential clock inputs (CK and CK)
- DLL aligns DQ and DQS transitions with CK transitions
- Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data
- Posted CAS by programmable additive latency for better command and data bus efficiency
- On-Die Termination (ODT) for better signal quality
- Synchronous ODT
- Dynamic ODT
- Asynchronous ODT
- Multi Purpose Register (MPR) for pre-defined pattern read out
- ZQ calibration for DQ drive and ODT
- RESET pin for Power-up sequence and reset function
- SRT range : Normal/extended
- Programmable Output driver impedance control
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 5.0915 | $ 5.09 |
| 10+ | $ 4.9767 | $ 49.77 |
| 30+ | $ 4.6645 | $ 139.94 |
| 100+ | $ 4.588 | $ 458.80 |
Standard Packaging2090/Full Tray | ||
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | Alliance Memory | |
| Packaging | FBGA-96(8x13) | |
| Operating Temperature | -40℃~+95℃ | |
| Features | Auto precharge function;Data mask function;Dynamic on-chip termination;ZQ calibration function;Asynchronous reset function | |
| Refresh Current | - | |
| Memory Size | 2Gbit | |
| Voltage - Supply | 1.283V~1.45V | |
| Clock Frequency | 800MHz | |
| Memory Format | DDR3L SDRAM | |
| Current - Supply | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | Alliance Memory | |
| Packaging | FBGA-96(8x13) | |
| Operating Temperature | -40℃~+95℃ | |
| Features | Auto precharge function;Data mask function;Dynamic on-chip termination;ZQ calibration function;Asynchronous reset function | |
| Refresh Current | - |
| Type | Description | |
|---|---|---|
| Memory Size | 2Gbit | |
| Voltage - Supply | 1.283V~1.45V | |
| Clock Frequency | 800MHz | |
| Memory Format | DDR3L SDRAM | |
| Current - Supply | - |
Help & FeedbackShow similar products (0) >
Features
AI Translation
- Double-data-rate architecture; two data transfers per clock cycle
- The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
- Bi-directional differential data strobe (DQS and DQS) is transmitted/ received with data for capturing data at the receiver
- DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
- Differential clock inputs (CK and CK)
- DLL aligns DQ and DQS transitions with CK transitions
- Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data
- Posted CAS by programmable additive latency for better command and data bus efficiency
- On-Die Termination (ODT) for better signal quality
- Synchronous ODT
- Dynamic ODT
- Asynchronous ODT
- Multi Purpose Register (MPR) for pre-defined pattern read out
- ZQ calibration for DQ drive and ODT
- RESET pin for Power-up sequence and reset function
- SRT range : Normal/extended
- Programmable Output driver impedance control
C570201 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
Alternative Parts
| MPN | Manufacturer | Packaging | Availability | Unit Price | ||
|---|---|---|---|---|---|---|
| AS4C128M16D3LB-12BCNTR | Alliance Memory | FBGA-96(8x13) | 0 | $ 8.5945 |