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Nexperia 74LVCH16245ADGVJ product image
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Nexperia 74LVCH16245ADGVJ

Manufacturer
MPN
74LVCH16245ADGVJ
LCSC Part #
C548888
Packaging
TSSOP-48-4.4mm
Customer #
Key Attributes
Schmitt trigger 1.2V~3.6V 16 2.4ns@3.3V,50pF TSSOP-48-4.4mm Buffers, Drivers, Receivers, Transceivers RoHS
DatasheetNexperia 74LVCH16245ADGVJ
RoHS Compliance1 documents available
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1+$ 1.4401$ 1.44
200+$ 0.5572$ 111.44
500+$ 0.5387$ 269.35
1,000+$ 0.5279$ 527.90
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers
ManufacturerNexperia
PackagingTSSOP-48-4.4mm
Input typeSchmitt trigger
Voltage - Supply1.2V~3.6V
Output TypeTri-State
Operating Temperature-40℃~+125℃
Quiescent Supply Current80uA
Current - Output High(IOH)24mA
Series74LVCH
Current - Output Low(IOL)24mA
Number of Bits per Element16
Channel TypeBidirectional
FeaturesPower-off isolation;Output enable;Level shifting;Bus hold
Number of Elements-
Propagation Delay2.4ns@3.3V,50pF

Introduction

AI Translation

The 74LVC16245A; 74LVCH16245A is a 16-bit transceiver with 3-state outputs. The device can be used as two 8-bit transceivers or one 16-bit transceiver. The device features two output enables (1OE and 2OE) each controlling eight outputs, and two send/receive (1DIR and 2DIR) inputs for direction control. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. The 74LVCH16245A bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.

Features

AI Translation
  • Overvoltage tolerant inputs to 5.5 V
  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low power dissipation
  • MULTIBYTE flow-through standard pin-out architecture
  • Low inductance multiple power and ground pins for minimum noise and ground bounce
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • All data inputs have bus hold (74LVCH16245A only)
  • Complies with JEDEC standard:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃

Applications

AI Translation
  • Level translation in mixed 3.3V and 5V environments