Nexperia 74LVC1G79GX,125

The 74LVC1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The lOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

• Wide supply voltage range from 1.65 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• CMOS low power dissipation
• ±24 mA output drive (VCC = 3.0 V)
• Direct interface with TTL levels
• Latch-up performance exceeds 250 mA
• IOFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V), JESD36 (4.5 V to 5.5 V)
• ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃

• Converter for mixed 3.3V and 5V environments