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MICROCHIP DSPIC33FJ256GP710-I/PF
| Manufacturer | |
| MPN | DSPIC33FJ256GP710-I/PF |
| LCSC Part # | C478989 |
| Packaging | TQFP-100(14x14) |
| Customer # | |
| Key Attributes | 16-Bit Digital Signal Controllers |
| Datasheet | MICROCHIP DSPIC33FJ256GP710-I/PF |
| RoHS Compliance | 2 documents available |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | TQFP-100(14x14) | |
| Operating Temperature | -40℃~+85℃ | |
| Clock Rate | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | TQFP-100(14x14) |
| Type | Description | |
|---|---|---|
| Operating Temperature | -40℃~+85℃ | |
| Clock Rate | - |
Help & FeedbackShow similar products (0) >
Features
AI Translation
- Up to 40 MIPS operation (at 3.0 - 3.6V): Industrial temperature range (-40°C to +85°C)
- Modified Harvard architecture
- C compiler optimized instruction set
- 16-bit wide data path
- 24-bit wide instructions
- Linear program memory addressing up to 4M instruction words
- Linear data memory addressing up to 64 Kbytes
- 83 base instructions: mostly 1 word/1 cycle
- Sixteen 16-bit General Purpose Registers
- Two 40-bit accumulators: With rounding and saturation options
- Flexible and powerful addressing modes: Indirect, Modulo and Bit-Reversed
- Software stack
- 16x16 fractional/integer multiply operations
- 32/16 and 16/16 divide operations
- Single-cycle multiply and accumulate: Accumulator write back for DSP operations, Dual data fetch
- Up to ±16-bit shifts for up to 40-bit data
- 8-channel hardware DMA
- 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)
- Most peripherals support DMA
- 5-cycle latency
- Up to 63 available interrupt sources
- Up to five external interrupts
- Seven programmable priority levels
- Five processor exceptions
- Up to 85 programmable digital I/O pins
- Wake-up/Interrupt-on-Change on up to 24 pins
- Output pins can drive from 3.0V to 3.6V
- All digital input pins are 5V tolerant
- 4 mA sink on all I/O pins
- Flash program memory, up to 256
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| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 15.0399 | $ 15.04 |
| 10+ | $ 14.4868 | $ 144.87 |
| 30+ | $ 13.5286 | $ 405.86 |
| 90+ | $ 12.6924 | $ 1142.32 |
Standard Packaging90/Full Tray | ||
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | TQFP-100(14x14) | |
| Operating Temperature | -40℃~+85℃ | |
| Clock Rate | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | TQFP-100(14x14) |
| Type | Description | |
|---|---|---|
| Operating Temperature | -40℃~+85℃ | |
| Clock Rate | - |
Help & FeedbackShow similar products (0) >
Features
AI Translation
- Up to 40 MIPS operation (at 3.0 - 3.6V): Industrial temperature range (-40°C to +85°C)
- Modified Harvard architecture
- C compiler optimized instruction set
- 16-bit wide data path
- 24-bit wide instructions
- Linear program memory addressing up to 4M instruction words
- Linear data memory addressing up to 64 Kbytes
- 83 base instructions: mostly 1 word/1 cycle
- Sixteen 16-bit General Purpose Registers
- Two 40-bit accumulators: With rounding and saturation options
- Flexible and powerful addressing modes: Indirect, Modulo and Bit-Reversed
- Software stack
- 16x16 fractional/integer multiply operations
- 32/16 and 16/16 divide operations
- Single-cycle multiply and accumulate: Accumulator write back for DSP operations, Dual data fetch
- Up to ±16-bit shifts for up to 40-bit data
- 8-channel hardware DMA
- 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)
- Most peripherals support DMA
- 5-cycle latency
- Up to 63 available interrupt sources
- Up to five external interrupts
- Seven programmable priority levels
- Five processor exceptions
- Up to 85 programmable digital I/O pins
- Wake-up/Interrupt-on-Change on up to 24 pins
- Output pins can drive from 3.0V to 3.6V
- All digital input pins are 5V tolerant
- 4 mA sink on all I/O pins
- Flash program memory, up to 256
C478989 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |