Intel/Altera FC80960HA33

The 80960Hx processor provides new performance levels while maintaining backward compatibility (pin and software) with the i960 CA/CF processor. This newest member of the family of i960 32-bit, RISC-style, embedded processors allows customers to create scalable designs that meet multiple price and performance points. The 80960Hx core is capable of issuing 150 million instructions per second, using a sophisticated instruction scheduler that allows the processor to sustain a throughput of two instructions every core clock, with a peak performance of three instructions per clock. The 80960Hx-series comprises three processors, which differ in the ratio of core clock speed to external bus speed. In addition to expanded clock frequency options, the 80960Hx provides essential enhancements for an emerging class of high-performance embedded applications. Features include a larger instruction cache, data cache, and data RAM than any other 80960 processor to date. It also boasts a 32-bit demultiplexed and pipelined burst bus, fast interrupt mechanism, guarded memory unit, wait state generator, dual programmable timers, ONCE and IEEE 1149.1-compliant boundary scan test and debug support, and new instructions.

• 32-Bit Parallel Architecture
• Load/Store Architecture
• Sixteen 32-Bit Global Registers
• Sixteen 32-Bit Local Registers
• 1.28 Gbyte Internal Bandwidth (80 MHz)
• On-Chip Register Cache
• 80960HA is 1x Bus Clock
• 80960HD is 2x Bus Clock
• 80960HT is zx Bus Clock
• Binary Compatible with Other 80960 Processors
• Issue Up To 150 Million Instructions per Second
• High-Performance On-Chip Storage
• 16Kbyte Four-Way Set-Associative Instruction Cache
• 8 Kbyte Four-Way Set-Associative Data Cache
• 2 Kbyte General Purpose RAM
• Separate 128-Bit Internal Paths For Instructions/Data
• 3.3 V Supply Voltage -- 5 V Tolerant Inputs -- TTL Compatible Outputs
• Guarded Memory Unit -- Provides Memory Protection
• User/Supervisor Read/Write/Execute
• 32-Bit Demultiplexed Burst Bus
• Per-Byte Parity Generation/Checking
• Address Pipelining Option
• Fully Programmable Wait State Generator
• Supports 8-, 16- or 32-Bit Bus Widths
• 160 Mbyte/s External Bandwidth (40 MHz)
• High-Speed Interrupt Controller
• Up to 240 External Interrupts
• 31 Fully Programmable Priorities
• Separate, Non-maskable Interrupt Pin
• Dual On-Chip 32-Bit Timers
• Auto Reload Capability and One-Shot
• CLKIN Prescaling, ÷1,2,4 or 8
• JTAG Support - IEEE 1149.1 Compliant
• Independent instruction paths inside the processor allow the execution of multiple, out-of-sequence instructions per clock.
• Register and resource scoreboarding interlocks maintain the logical integrity of sequential instructions that are being executed in parallel.
• To sustain execution of multiple instructions in each clock cycle, the processor decodes multiple instructions in parallel and simultaneously issues these instructions to parallel processing units.
• The various processing units are then able to independently access instruction operands in parallel from a common register set.
• Local Register Cache integrated on-chip provides automatic register management on call/return instructions.
• The 80960Hx supports the 80960 architecturally-defined branch prediction mechanism.
• A 32-bit high performance bus controller interfaces the 80960Hx core to the external memory and peripherals. The Bus Control Unit features a maximum transfer rate of 160 Mbytes per second.