Infineon/CYPRESS CY7C1020B-12VC

This device is a high-performance CMOS static random access memory organized as 32,768 words × 16 bits. It features an automatic power-down function that significantly reduces power consumption when deselected. Write operations are performed by bringing the chip enable and write enable inputs low. If byte low enable is low, data is written from the I/O pins to the location specified by the address pins. If byte high enable is low, data is written from the I/O pins. Read operations are performed by bringing the chip enable and output enable low while holding the write enable high. If byte low enable is low, the data of the memory cell specified by the address pins will appear on the I/O pins. If byte high enable is high, the stored data will appear on the I/O pins. The I/O pins are in a high-impedance state when the device is deselected, the output is disabled, byte high enable and byte low enable are disabled, or during a write operation. The device is available in standard 44-pin TSOP Type II and 44-pin wide-body SOJ packages.

• High speed, access time tAA of 12.15 ns
• CMOS technology for optimized speed and power consumption
• Low operating power, 825 mW maximum
• Low CMOS standby power, 16.5 mW maximum
• Automatic power-down when deselected
• Independent upper and lower byte control
• Available in lead-free and non-lead-free 44-pin TSOP II and 44-pin wide-body SOJ packages