Infineon/CYPRESS CY7C1362C-166AJXCKJ

The Cypress synchronous burst SRAM series features a high-speed, low-power CMOS design utilizing advanced three-layer polysilicon, dual-layer metal technology. Each memory cell consists of four transistors and two high-value resistors. The CY7C1360A and CY7C1362A SRAMs integrate 262,144 × 36 and 524,288 × 18 SRAM cells, respectively, with advanced synchronous peripheral circuits and a 2-bit counter for internal burst operations. All synchronous inputs are strobed by registers controlled by a positive edge-triggered clock input (CLK). Asynchronous inputs include output enable (OE) and burst mode control (MODE); data outputs (Q) are enabled by OE and are also asynchronous. Address and chip select are registered through the address status processor (ADSP) or address status controller (ADSC) input pins. Address, data inputs, and write control are registered on-chip to initiate self-timed write cycles. For BGA and TQFP AJ package versions, four pins are used to implement JTAG test functionality. The CY7C1360A and CY7C1362A operate from a +3.3V supply, with all inputs and outputs compatible with LVTTL.

• Fast access time: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 225, 200, 166, and 150 MHz
• Fast OE access time: 2.5 ns, 3.0 ns, and 3.5 ns
• Suitable for depth expansion (one-cycle chip select deselect to eliminate bus contention)
• 3.3V -5% and +10% supply
• 3.3V or 2.5V I/O supply
• 5V-tolerant inputs except I/O
• Clamp diodes on all inputs and outputs to VSS
• Common data input and data output
• Byte write enable and global write control
• Multiple chip select enables for depth expansion: three chip select enables for A package version, two chip select enables for BG and AJ package versions
• Address pipelining capability
• Address, data, and control registers
• Internal self-timed write cycle
• Burst control pin (interleaved or linear burst sequence)
• Automatic power-down via ZZ mode or CE deselect
• JTAG boundary scan on BG and AJ package versions
• Thin 119-bump, 14 mm × 22 mm PBGA and 100-pin TQFP packages

• System L2 cache