Infineon/CYPRESS CY7C429-25AC
| Manufacturer | |
| MPN | CY7C429-25AC |
| LCSC Part # | C2954697 |
| Packaging | TQFP-32(7x7) |
| Customer # | |
| Key Attributes | 2Kx9 25ns 50mA 4.5V~5.5V 28.5MHz TQFP-32(7x7) FIFOs Memory |
| Datasheet | Infineon/CYPRESS CY7C429-25AC |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/FIFOs Memory | |
| Manufacturer | Infineon/CYPRESS | |
| Packaging | TQFP-32(7x7) | |
| Memory Size | 2Kx9 | |
| Access Time | 25ns | |
| Current - Supply(Max) | 50mA | |
| Voltage - Supply | 4.5V~5.5V | |
| Features | Automatic retransmission function;Output enable | |
| Clock Frequency | 28.5MHz | |
| Operating Temperature | 0℃~+70℃ | |
| Function | Asynchronous | |
| Bus Directional | Unidirectional | |
| Programmable Flags Support | No |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/FIFOs Memory | |
| Manufacturer | Infineon/CYPRESS | |
| Packaging | TQFP-32(7x7) | |
| Memory Size | 2Kx9 | |
| Access Time | 25ns | |
| Current - Supply(Max) | 50mA | |
| Voltage - Supply | 4.5V~5.5V |
| Type | Description | |
|---|---|---|
| Features | Automatic retransmission function;Output enable | |
| Clock Frequency | 28.5MHz | |
| Operating Temperature | 0℃~+70℃ | |
| Function | Asynchronous | |
| Bus Directional | Unidirectional | |
| Programmable Flags Support | No |
Introduction
CY7C420/CY7C421, CY7C424/CY7C425, and CY7C428/CY7C429 are first-in first-out (FIFO) memories available in 600-mil wide and 300-mil wide packages. They are 512, 1024, and 2048 words deep, respectively, and 9 bits wide. Each FIFO memory is organized so that data is read out in the same order it was written in. Full and empty flags are provided to prevent overflow and underflow. Three additional pins are provided to allow unlimited expansion in width, depth, or both. The depth expansion technique routes control signals from one device to another in parallel, eliminating the serial accumulation of propagation delays so that throughput is not reduced. Data is routed in a similar manner. Read and write operations can be asynchronous, with each operating at rates up to 33.3 MHz. A write operation occurs when the write signal (W̄) is LOW. A read operation occurs when the read signal (R̄) is LOW. When R̄ is HIGH, the nine data outputs enter a high-impedance state. A half-full (HF) output flag is provided, which is active in standalone and width expansion configurations. In depth expansion configurations, this pin provides expansion output (XO) information to inform the next FIFO that it will be activated. In standalone and width expansion configurations, asserting the retransmit (RT) input LOW causes the FIFO to retransmit data. During retransmission, both the read enable (R̄) and write enable (W̄) must be HIGH, after which R̄ is used to access the data. CY7C420, CY7C421, CY7C424, CY7C425, CY7C428, and CY7C429 are fabricated using advanced 0.8-micron N-well CMOS technology. Input ESD protection exceeds 2000V, and latch-up is prevented through carefully designed guard rings and substrate bias generators.
Features
- 512×9, 1024×9, 2048×9 FIFO buffer memory
- Dual-port RAM cell
- Asynchronous read/write
- High-speed 33.3 MHz read/write, independent of depth/width
- Low operating power consumption
- I CC (max) = 142 mA (commercial)
- I CC (max) = 147 mA
- Half-full flag in independent mode
- Empty and full flags
- Retransmit function in independent mode
- Width and depth expandable
- Parallel cascading minimizes fall-through delay
- 5 V ± 10% supply
- 300-mil DIP package
- 300-mil SOJ package
- TTL compatible
- Three-state outputs
- Pin-compatible and functionally equivalent to IDT7201, IDT7202, and IDT7203
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 0.9119 | $ 0.91 |
| 200+ | $ 0.3534 | $ 70.68 |
| 500+ | $ 0.341 | $ 170.50 |
| 1,000+ | $ 0.3349 | $ 334.90 |
Standard Packaging25/Full Tube | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/FIFOs Memory | |
| Manufacturer | Infineon/CYPRESS | |
| Packaging | TQFP-32(7x7) | |
| Memory Size | 2Kx9 | |
| Access Time | 25ns | |
| Current - Supply(Max) | 50mA | |
| Voltage - Supply | 4.5V~5.5V | |
| Features | Automatic retransmission function;Output enable | |
| Clock Frequency | 28.5MHz | |
| Operating Temperature | 0℃~+70℃ | |
| Function | Asynchronous | |
| Bus Directional | Unidirectional | |
| Programmable Flags Support | No |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/FIFOs Memory | |
| Manufacturer | Infineon/CYPRESS | |
| Packaging | TQFP-32(7x7) | |
| Memory Size | 2Kx9 | |
| Access Time | 25ns | |
| Current - Supply(Max) | 50mA | |
| Voltage - Supply | 4.5V~5.5V |
| Type | Description | |
|---|---|---|
| Features | Automatic retransmission function;Output enable | |
| Clock Frequency | 28.5MHz | |
| Operating Temperature | 0℃~+70℃ | |
| Function | Asynchronous | |
| Bus Directional | Unidirectional | |
| Programmable Flags Support | No |
Introduction
CY7C420/CY7C421, CY7C424/CY7C425, and CY7C428/CY7C429 are first-in first-out (FIFO) memories available in 600-mil wide and 300-mil wide packages. They are 512, 1024, and 2048 words deep, respectively, and 9 bits wide. Each FIFO memory is organized so that data is read out in the same order it was written in. Full and empty flags are provided to prevent overflow and underflow. Three additional pins are provided to allow unlimited expansion in width, depth, or both. The depth expansion technique routes control signals from one device to another in parallel, eliminating the serial accumulation of propagation delays so that throughput is not reduced. Data is routed in a similar manner. Read and write operations can be asynchronous, with each operating at rates up to 33.3 MHz. A write operation occurs when the write signal (W̄) is LOW. A read operation occurs when the read signal (R̄) is LOW. When R̄ is HIGH, the nine data outputs enter a high-impedance state. A half-full (HF) output flag is provided, which is active in standalone and width expansion configurations. In depth expansion configurations, this pin provides expansion output (XO) information to inform the next FIFO that it will be activated. In standalone and width expansion configurations, asserting the retransmit (RT) input LOW causes the FIFO to retransmit data. During retransmission, both the read enable (R̄) and write enable (W̄) must be HIGH, after which R̄ is used to access the data. CY7C420, CY7C421, CY7C424, CY7C425, CY7C428, and CY7C429 are fabricated using advanced 0.8-micron N-well CMOS technology. Input ESD protection exceeds 2000V, and latch-up is prevented through carefully designed guard rings and substrate bias generators.
Features
- 512×9, 1024×9, 2048×9 FIFO buffer memory
- Dual-port RAM cell
- Asynchronous read/write
- High-speed 33.3 MHz read/write, independent of depth/width
- Low operating power consumption
- I CC (max) = 142 mA (commercial)
- I CC (max) = 147 mA
- Half-full flag in independent mode
- Empty and full flags
- Retransmit function in independent mode
- Width and depth expandable
- Parallel cascading minimizes fall-through delay
- 5 V ± 10% supply
- 300-mil DIP package
- 300-mil SOJ package
- TTL compatible
- Three-state outputs
- Pin-compatible and functionally equivalent to IDT7201, IDT7202, and IDT7203
C2954697 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |

