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Infineon/CYPRESS S25FL512SAGMFIR11J product image
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Infineon/CYPRESS S25FL512SAGMFIR11J

Manufacturer
Infineon/CYPRESS
MPN
S25FL512SAGMFIR11J
LCSC Part #
C2951817
Packaging
SOIC-16
Customer #
Key Attributes
512Mbit 2.7V~3.6V SPI SOIC-16 Memory
DatasheetInfineon/CYPRESS S25FL512SAGMFIR11J
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QtyUnit Price(Reference Only)Total Amount
1+$ 0.4443$ 0.44
200+$ 0.172$ 34.40
500+$ 0.1659$ 82.95
1,000+$ 0.1629$ 162.90
Standard Packaging500/Full Reel
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory
ManufacturerInfineon/CYPRESS
PackagingSOIC-16
Operating Temperature-40℃~+85℃
FeaturesPower-on reset;Hardware write protection;Software write protection;ECC error correction
Memory Size512Mbit
Voltage - Supply2.7V~3.6V
Program / Erase Cycles100,000 cycles
Data Retention - TDR (Year)20 Years
Block Erase Time(tBE)500ms@(256KB)
Page Programming Time (Tpp)340us
InterfaceSPI
Standby Supply Current70uA
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Introduction

AI Translation

Cypress S25FL512S device is a flash nonvolatile memory product using:

  • MirrorBit technology - that stores two data bits in each memory array transistor
  • Eclipse architecture - that dramatically improves program and erase performance
  • 65 nm process lithography This device connects to a host system via a Serial Peripheral Interface (SPI).

Features

AI Translation
  • CMOS 3.0 Volt Core with versatile I/O
  • Serial Peripheral Interface (SPI) with Multi-I/O
  • Density: 512 Mbits (64 Mbytes)
  • SPI:
    • SPI Clock polarity and phase modes 0 and 3
    • Double Data Rate (DDR) option
    • Extended Addressing: 32-bit address
    • Serial Command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families
    • Multi I/O Command set and footprint compatible with the S25FL-P SPI family
  • READ Commands:
    • Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
    • AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected address
    • Common Flash Interface (CFI) data for configuration information.
  • Programming (1.5 MBps):
    • 512-byte Page Programming buffer
    • Quad-Input Page Programming (QPP) for slow clock systems
    • Automatic ECC - internal hardware Error Correction Code generation with single bit error correction
  • Erase (0.5 to 0.65 MBps):
    • Uniform 256-kbyte sectors
  • Cycling Endurance:
    • 100,000 Program-Erase Cycles, minimum
  • Data Retention:
    • 20-Year Data Retention, minimum
  • Security features:
    • OTP array of 1024 bytes
    • Block Protection:
      • Status Register bits to control protection against program or erase of a contiguous range of sectors.
      • Hardware and software control options
    • Advanced Sector Protection (ASP):
      • Individual sector protection controlled by boot code or password
  • Cypress 65 nm MirrorBit Technology with Eclipse Architecture
  • Core supply voltage: 2.7 V to 3.6 V
  • I/O supply voltage: 1.65 V to 3.6 V
    • SO16 and FBGA packages
  • Temperature range:
    • Industrial: -40 ℃ to +85 ℃
    • Industrial Plus: -40 ℃ to +105 ℃
    • Automotive, AEC-Q100 Grade 3: -40 ℃ to +85 ℃
    • Automotive, AEC-Q100 Grade 2: -40 ℃ to +105 ℃
    • Automotive, AEC-Q100 Grade 1: -40 ℃ to +125 ℃
  • Packages (all Pb-free):
    • 16-pin SOIC (300 mil)
    • 24-BGA (6x8 mm)
      • 5x5 ball (FAB024) and 4x6 ball (FAC024) footprint options
    • Known Good Die and Known Tested Die