Infineon/CYPRESS S70FS01GSAGMFI010

The Spansion FS - S Family devices are Flash non - volatile memory products using:

• MirrorBit technology - that stores two data bits in each memory array transistor
• Eclipse architecture - that dramatically improves program and erase performance
• 65 nm process lithography

The FS - S Family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) or QPI, also known as Quad Peripheral Interface (QPI) serial commands. This multiple width interface is called SPI Multi - I/O or MIO. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock.

The FS - S Eclipse architecture features a Page Programming Buffer that allows up to 512 - bytes to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.

Executing code directly from Flash memory is often called Execute - In - Place or XIP. By using FS - S Family devices at the higher clock rates supported, with Quad or DDR - Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.

The FS - S Family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or embedded applications. They are an excellent solution for systems with limited space, signal connections, and power. They are ideal for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data.

The S70FS01GS device is a dual die stack of two FS512S die.

The FS - S Family is command subset and footprint compatible with prior generation FL - S, FL1 - K and FL - P families. However, the power supply and interface voltages are nominal 1.8V.

• SPI Clock polarity and phase modes 0 and 3
• Double Data Rate (DDR)
• Extended Addressing - 24 or 32 - bit address options
• Serial Command subset & footprint compatible with , S25FL1 - K, S25FL - P, and S25FL - S SPI families
• Multi I/O Command subset & footprint compatible with S25FL - P, S25FL1 - K and S25FL - S SPI families
• Commands: Normal, Fast, Dual I/O, Quad I/O, DDR Quad I/O
• Modes: Burst Wrap, Continuous (XIP), QPI (QPI)
• Serial Flash Discoverable Parameters (SFDP) and Common Flash Interface (CFI), for configuration information.
• 256 or 512 Bytes Page Programming buffer
• Program suspend and resume
• Hybrid sector option
• Physical set of eight 4 KBytes sectors and one 224 KBytes sector at the top or bottom of address space with all remaining sectors of 256 KBytes
• Uniform sector option
• Physical uniform 256 KBytes blocks
• Erase suspend and resume
• Erase status evaluation
• 100,000 Program - Erase Cycles on any sector, min
• 20 Year Data Retention, typical
• One Time Program (OTP) array of 1024 bytes
• Block Protection:
  • Status Register bits to control protection against program or erase of a contiguous range of sectors.
  • Hardware and software control options
• Advanced Sector Protection (ASP)
  • Individual sector protection controlled by boot code or password
  • Option for password control of read access
• Spansion 65 nm MirrorBit Technology with Eclipse Architecture
• Supply Voltage – 1.7V to 2.0V
• Temperature Range
  • Industrial (-40℃ to +85℃)
  • Industrial Plus (-40℃ to +105℃)
• Packages (all Pb - free)
  • 16 - lead SOIC 300 mil
  • BGA - 24 6x8 mm
  • 5x5 ball footprint