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Infineon/CYPRESS CY9AF112KQN-G-AVE2 product image
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Infineon/CYPRESS CY9AF112KQN-G-AVE2

Manufacturer
MPN
CY9AF112KQN-G-AVE2
LCSC Part #
C2948121
Packaging
VFQFN-48-EP
Customer #
Key Attributes
ARM Cortex-M3 32 Bit 40MHz VFQFN-48-EP Microcontrollers RoHS
DatasheetInfineon/CYPRESS CY9AF112KQN-G-AVE2
RoHS Compliance1 documents available
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement
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QtyUnit Price(Reference Only)Total Amount
1+$ 0.537$ 0.54
200+$ 0.2084$ 41.68
500+$ 0.2006$ 100.30
1,000+$ 0.1976$ 197.60
Standard Packaging2600/Full Tray
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microcontrollers
ManufacturerInfineon/CYPRESS
PackagingVFQFN-48-EP
ADC (Bit)12bit
Number of I/O36
Operating Temperature-40℃~+105℃
Program Memory TypeFLASH
Voltage - Supply2.7V~5.5V
EEPROM-
Program Storage Size160KB
CPU CoreARM Cortex-M3
Core Size32 Bit
CPU Maximum Speed40MHz
Oscillator TypeBuilt-in

Introduction

AI Translation

The MB9A110K Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and low cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I2C, LIN).

Features

AI Translation
  • 32-bit ARM Cortex-M3 Core
  • Processor version: r2p1
  • Up to 40 MHz Frequency Operation
  • Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels
  • On-chip Memories
  • [Flash memory]
  • This Series are based on two independent on-chip Flash memories.
  • MainFlash: Up to 128 KB, Read cycle: 0 wait-cycle, Security function for code protection
  • Multi-function Serial Interface (Max 4 channels)
  • 2 channels with 16-steps × 9 -bits FIFO (ch.0, ch.1), 2 channels without FIFO (ch.3, ch.5)
  • Operation mode is selectable from the followings for each channel. (In ch.5, only UART and LIN are available.)
  • UART
  • CSIO
  • LIN
  • I2C
  • [UART]
  • WorkFlash: 32 KB, Read cycle: 0 wait-cycle, Security function is shared with code protection
  • [SRAM]
  • This Series contain a total of up to 16 KB on-chip SRAM. This is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of CortexM3 core. SRAM1 is connected to System bus.
  • SRAM0: 8 KB, SRAM1: 8 KB, Full-duplex double buffer
  • [LIN]
  • LIN protocol Rev.2.1 supported
  • Full-duplex double buffer
  • Master/Slave mode supported
  • LIN break field generate (can be changed 13 to 16-bit length)
  • LIN break delimiter generate (can be changed 1 to 4-bit length)
  • Various error detect functions available (parity errors, framing errors, and overrun errors)
  • [I2C]
  • Standard mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
  • DMA Controller (4 channels)
  • DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
  • 8 independently configured and operated channels
  • Transfer can be started by software or request from the builtin peripherals
  • Transfer address area: 32-bit (4 GB)
  • Transfer mode: Block transfer/Burst transfer/Demand transfer
  • Transfer data type: byte/half-word/word
  • Transfer block count: 1 to 16
  • Number of transfers: 1 to 65536
  • A/D Converter (Max 8 channels)
  • [12-bit A/D Converter]
  • Successive Approximation Register type
  • Built-in 2 unit
  • Conversion time: 1.0 μs @ 5 ν
  • Priority conversion available (priority at 2 levels)
  • Scanning conversion mode
  • Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps)
  • Base Timer (Max 8 channels)
  • Operation mode is selectable from the followings for each channel.
  • 16-bit PWM timer
  • 16-bit PPG timer
  • 16-/32-bit reload timer
  • 16-/32-bit PWC timer
  • General Purpose I/O Port
  • This series can use its pins as General Purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated.
  • Capable of pull-up control per pin
  • Capable of reading pin level directly
  • Built-in the port relocate function
  • Up 36 fast General Purpose I/O Ports
  • Multi-function Timer
  • The Multi-function timer is composed of the following blocks.
  • 16-bit free-run timer × 3 ch.
  • Input capture × 4 ch.
  • Output compare × 6 ch.
  • A/D activating compare × 3 ch.
  • Waveform generator × 3 ch.
  • 16-bit PPG timer × 3 ch.
  • The following function can be used to achieve the motor control.
  • PWM signal output function
  • DC chopper waveform output function
  • Dead time function
  • Input capture function
  • A/D convertor activate function
  • DTIF (Motor emergency stop) interrupt function
  • Real-time clock (RTC)
  • The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99.
  • Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.
  • Capable of rewriting the time with continuing the time count.
  • Quadrature Position/Revolution Counter (QPRC)
  • The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter.
  • The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
  • 16-bit position counter
  • 16-bit revolution counter