SILICON LABS SI5340D-D10593-GMR

The any-frequency, any-output Si5341/40 clock generators combine a wide-band PLL with proprietary MultiSynth fractional synthesizer technology to offer a versatile and high performance clock generator platform. This highly flexible architecture is capable of synthesizing a wide range of integer and non-integer related frequencies up to 1 GHz on 10 differential clock outputs while delivering sub-100 fs rms phase jitter performance with 0 ppm error. Each of the clock outputs can be assigned its own format and output voltage enabling the Si5341/40 to replace multiple clock ICs and oscillators with a single device making it a true "clock tree on a chip." The Si5341/40 can be quickly and easily configured using ClockBuilderPro software. Custom part numbers are automatically assigned using a ClockBuilder Pro for fast, free, and easy factory pre-programming or the Si5341/40 can be programmed via I²C and SPI serial interfaces. The Si5340/41-D combines a wide band PLL with next generation MultiSynth technology to offer the industry's most versatile and high performance clock generator. The PLL locks to either an external crystal between XA/XB or to an external clock connected to XA/XB or IN0, 1, 2. A fractional or integer multiplier takes the selected input clock or cystal frequency up to a very high frequency that is then divided by the MultiSynth output stage to any frequency in the range of 100 Hz to 1 GHz on each output. The MultiSynth stage can divide by both integer and fractional values. The high-resolution fractional MultiSynth dividers enable true any-frequency input to any-frequency on any of the outputs.

• Generates any combination of output frequencies from any input frequency
• Ultra-low jitter of 90 fs rms
• Input frequency range:
  • External crystal: 25 to 54 MHz
  • Differential clock: 10 to 750 MHz
  • LVCMOS clock: 10 to 250 MHz
• Output frequency range:
  • Differential: 100 Hz to 1028 MHz
  • LVCMOS: 100 Hz to 250 MHz
• Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable signal amplitude
• Locks to gapped clock inputs
• Optional zero delay mode
• Glitchless on the fly output frequency changes
• DCO mode: as low as 0.001 ppb steps
• Core voltage
  • VDD: 1.8 ±5%
  • VDDA: 3.3 ±5%
• Independent output clock supply pins
  • 3.3 V, 2.5 V, or 1.8 V
• Serial interface: I²C or SPI
• In-circuit programmable with non-volatile OTP memory
• ClockBuilder Pro software simplifies device configuration
• Temperature range: -40 to +85 ℃
• Pb-free, RoHS-6 compliant

• Clock tree generation replacing XOs, buffers, signal format translators
• Any-frequency clock translation
• Clocking for FPGAs, processors, memory
• Ethernet switches/routers
• OTN framers/mappers/processors
• Test equipment and instrumentation
• Broadcast video