ROHM ML62Q1700-NNNTBZ0BX

ML62Q1700 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and integrated with program memory(Flash memory), data memory(RAM), data Flash and rich peripheral functions such as the multiplier/divider, CRC operator, DMA controller, clock generator, Simplified RTC, timer, UART, synchronous serial port, I²C bus interface unit, buzzer, Voltage Level Supervisor(VLS), successive approximation type A/D converter, D/A converter, analog comparator, LCD driver, safety function(IEC60730/60335 Class B) and etc. The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by pipeline architecture parallel processing. The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming) function supports the Flash programming in production line. The ML62Q1700 Group has seven packages (48pin - 100pin) and ten kinds of memory sizes(32Kbyte - 512Kbyte).

• CPU
  • 16-bit RISC CPU: nX-U16/100(A35 core) Instruction system: 16-bit length instruction Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
  • On-chip debug function built-in (supported by LAPIS on-chip debug emulator EASE1000)
  • ISP (In-System Programming) function built-in
  • Minimum instruction execution time 30.5 μs (at 32.768 kHz system clock) 62.5ns/41.6ns (at 16 MHz/24MHz system clock)
• Coprocessor for multiplication and division
  • Multiplication: 16bit × 16bit (operation time 4 cycles)
  • Division: 32bit / 16bit (operation time 8 cycles)
  • Division: 32bit / 32bit (operation time 16 cycles)
  • Multiply-accumulate (non-saturating): 16bit×16bit + 32bit (operation time 4 cycles)
  • Multiply-accumulate (saturating): 16bit×16bit + 32bit (operation time 4 cycles)
• Operating voltage and temperature
  • Operating voltage: VDD = 1.6 to 5.5 V （Need 1.8V or higher at the power on）
  • Operating temperature: -40 to +105 ℃
• Internal memory
  • Program Flash memory area
    • Rewrite count: 100 cycles
    • Rewrite unit: 32bit(4byte)
    • Erase unit: 16Kbyte/1Kbyte
    • Erase/Rewrite temperature: 0℃ to +40℃
  • Data Flash memory area
    • Rewrite count 10,000 cycles
    • Rewrite unit: 8bit(1byte)
    • Erase unit: all area/128byte
    • Erase/Rewrite temperature: -40℃ to +85℃
    • Back Ground Operation(BGO) : CPU can work while erasing and rewriting.
  • Data RAM area
    • Rewrite unit: 8bit/16bit(1byte/2byte)
    • Parity check function (Parity error reset or interrupt is generatable)
• Clock
  • Low-speed clock
    • Internal low-speed RC oscillation: Approx.32.768 kHz
    • External low-speed crystal oscillation: 32.768 kHz crystal resonator is connectable
    • 3 modes is available for the crystal oscillation
      • Tough mode: Largest oscillation allowance to make highest resistance against leakage between the pins
      • Standard mode: Standard oscillation allowance and current consumption
      • Low power current mode: Smaller oscillation allowance than standard mode to make lower current consumption
  • High-speed clock
    • PLL oscillation: 24MHz/16MHz is selectable by code option
  • WDT(Watch Dog Timer) clock
    • Internal low-speed RC oscillation: Approx. 1kHz
    • The WDT independent clock or the divided clock of internal low-speed clock is selectable by the code option.
• Reset
  • RESET_N pin reset
  • Reset by power-on detection
  • Reset by the 2nd watchdog timer (WDT) overflow
  • Reset by WDT counter clear during the clear invalid period
  • Reset by RAM parity error
  • Reset by unused ROM access
  • Reset by voltage level detection (VLS)
  • The software reset by BRK instruction (reset CPU only)
  • Reset to the peripheral circuits by Block Reset Control Registers (BRECON 0 to 3)
  • One-time reset to the all peripheral circuits by Software Reset Control Register (SOFTRCON)
• Power management
  • HALT mode: CPU stops executing instruction, clock oscillations and peripheral circuits remain previous states
  • HALT-H mode: CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits working with low-speed clock remain previous states
  • STOP mode: CPU stops executing instruction, both high-speed oscillation and low-speed oscillation stop.
  • STOP-D mode: CPU stops executing instruction, both high-speed oscillation and low-speed oscillation stop. The internal regulator’s output voltage (VDDL) goes down to reduce the current consumption.
  • Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8, 1/16 or 1/32 of the oscillation clock)

• LCD driving
• Temperature sensing
• Infrared communication
• Voltage monitoring
• Data acquisition
• Timer control
• Serial communication
• I2C communication
• Buzzer control
• Analog signal processing
• Digital signal processing
• Low-power applications
• Real-time clock
• Security functions
• In-circuit programming
• Built-in debugging
• Motor control
• Industrial automation
• Home appliances
• Medical devices
• Consumer electronics
• Automotive electronics
• Power management