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Alliance Memory AS7C4096A-15TINTR

Produttore
Cod. Prod.
AS7C4096A-15TINTR
Cod. LCSC
C7217876
Imballo
TSOP-442
Numero Cliente
Attr. chiave
4Mbit Parallel Port (Parallel) TSOP-442 Memory RoHS
Scheda TecnicaAlliance Memory AS7C4096A-15TINTR
Parti alternative5
Esaurito
Avvisami
Minimo: 1Multiplo: 1Unità di vendita: Piece
Aggiungi alla Lista BOM
QtàPr. unit.(Solo per riferimento)Importo totale
1+$ 11.0867$ 11.09
200+$ 4.4235$ 884.70
500+$ 4.2765$ 2138.25
1,000+$ 4.2038$ 4203.80
Package Standard1000/Full Reel
Prezzo migliore per quantità maggiore?
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Specifiche del Prodotto

Tutto
TipoDescrizione
CategoriaIntegrated Circuits (ICs)/Memory/Memory
ProduttoreAlliance Memory
ImballoTSOP-442
Operating Temperature-40℃~+85℃
FeaturesAuto power-down function
Memory Size4Mbit
Voltage - Supply4.5V~5.5V;120mA
Access Time15ns
InterfaceParallel Port (Parallel)
Standby Supply Current10mA

Descrizione

Traduzione AI

The AS7C4096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA,tRC,tWC) of 10/12/15/20 ns with output enable access times (ΔtoE) of 5/6 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high the device enters standby mode. The device is guaranteed not to exceed 55mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1 - I/O8 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5.0V supply voltage. This device is available as per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.

Caratteristiche

Traduzione AI
  • Pin compatible to AS7C4096
  • Industrial and commercial temperature
  • Organization: 524,288 words x 8 bits
  • Center power and ground pins
  • High speed - 10/12/15/20 ns address access time - 5/6 ns output enable access time
  • Low power consumption: ACTIVE - 880mW/max @ 10 ns
  • Low power consumption: STANDBY - 55mW/max CMOS
  • Equal access and cycle times
  • Easy memory expansion with CE, OE inputs
  • TTL-compatible, three-state I/O
  • JEDEC standard packages - 400 mil 36-pin SOJ - 44-pin TSOP 2
  • ESD protection ≥2000 volts
  • Latch-up current ≥200 mA

Parti alternative

MPNProduttoreImballaggioDisponibilitàPrezzo unitario
AS7C4096A-15TINAlliance MemoryTSOP-4420$ 12.1847
AS7C4098A-20TINAlliance MemoryTSOP-4420$ 11.4178
AS7C4096A-20TINAlliance MemoryTSOP-4420$ 12.824
AS7C4098A-20TCNTRAlliance MemoryTSOP-4420$ 12.5791
AS7C4096A-20TCNAlliance MemoryTSOP-4420$ 12.824