Infineon/CYPRESS CY7C1371C-117BGC

CY7C1371C/CY7C1373C is a synchronous flow-through burst SRAM designed to eliminate wait states during write-to-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified by the Clock Enable input (CEN). If CEN is HIGH, the clock is not recognized and all internal states remain unchanged. All synchronous operations are qualified by CEN. The maximum access delay from the rising clock edge (tCDV) is 6.5 ns (133 MHz device). Access can be initiated by asserting all three chip enables (CE1̄, CE2, CE3̄) at the rising clock edge. Write operations are qualified by Write Enable (WE). Three synchronous chip enables (CE1̄, CE2, CE3̄) and one asynchronous Output Enable (OE) simplify depth expansion. All operations (read, write, and deselect) are pipelined.

• No Bus Latency (NoBL™) architecture eliminates dead cycles between write and read cycles
• Supports bus operation up to 133 MHz, zero wait states, data transferred on every clock
• Pin-compatible with ZBT™ devices, functionally equivalent
• Internal self-timed output buffer control, no OE required
• Registered inputs for flow-through operation
• Byte write capability
• 3.3V/2.5V I/O supply
• Fast clock-to-output time: 6.5 ns (133 MHz devices); 7.5 ns (117 MHz devices); 8.5 ns (100 MHz devices)
• Clock Enable (CEN) pin for enabling clock and pausing operation
• Synchronous self-timed write
• Asynchronous output enable
• Available in JEDEC standard 100 TQFP, 119-ball BGA, and 165-ball fBGA packages
• Three chip enables for easy depth expansion
• Automatic power-down via ZZ mode or CE deselect
• JTAG boundary scan on BGA and fBGA packages
• Burst capability — linear or interleaved burst order
• Low standby power consumption