Alliance Memory AS4C1G8D3LA-10BAN
| Hersteller | |
| Herst.-Teilenr. | AS4C1G8D3LA-10BAN |
| LCSC-Nr. | C17452575 |
| Verp. | FBGA-78(9x10.5) |
| Kundennummer | |
| Hauptmerkm. | 8Gbit 933MHz DDR3L SDRAM FBGA-78(9x10.5) Memory |
| Datenblatt | Alliance Memory AS4C1G8D3LA-10BAN |
| Alternativteile | 4 |
Produktspezifikationen
Alle
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Memory/Memory | |
| Hersteller | Alliance Memory | |
| Verp. | FBGA-78(9x10.5) | |
| Operating Temperature | -40℃~+105℃ | |
| Features | Auto precharge function;Data mask function;Dynamic on-chip termination;ZQ calibration function;Asynchronous reset function | |
| Refresh Current | 24mA | |
| Memory Size | 8Gbit | |
| Voltage - Supply | 1.283V~1.45V;96mA | |
| Clock Frequency | 933MHz | |
| Memory Format | DDR3L SDRAM |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Memory/Memory | |
| Hersteller | Alliance Memory | |
| Verp. | FBGA-78(9x10.5) | |
| Operating Temperature | -40℃~+105℃ | |
| Features | Auto precharge function;Data mask function;Dynamic on-chip termination;ZQ calibration function;Asynchronous reset function |
| Typ | Beschreibung | |
|---|---|---|
| Refresh Current | 24mA | |
| Memory Size | 8Gbit | |
| Voltage - Supply | 1.283V~1.45V;96mA | |
| Clock Frequency | 933MHz | |
| Memory Format | DDR3L SDRAM |
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Merkmale
KI-Übersetzung
- Double-data-rate architecture; two data transfers per clock cycle
- The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
- Bi-directional differential data strobe (DQS and DQS) is transmitted/ received with data for capturing data at the receiver
- DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
- Differential clock inputs (CK and CK)
- DLL aligns DQ and DQS transitions with CK transitions
- Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data
- Posted CAS by programmable additive latency for better command and data bus efficiency
- On-Die Termination (ODT) for better signal quality
- Synchronous ODT
- Dynamic ODT
- Asynchronous ODT
- Multi Purpose Register (MPR) for pre-defined pattern read out
- ZQ calibration for DQ drive and ODT
- RESET pin for Power-up sequence and reset function
- SRT range : Normal/extended
- Programmable Output driver impedance control
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Zur BOM-Liste hinzufügen
| Stk. | E-Preis(Nur als Referenz) | Gesamtbetrag |
|---|---|---|
| 1+ | $ 57.9571 | $ 57.96 |
| 220+ | $ 23.1256 | $ 5087.63 |
| 440+ | $ 22.3525 | $ 9835.10 |
| 1,100+ | $ 21.9715 | $ 24168.65 |
Standardgehäuse220/Full Tray | ||
Besserer Preis bei größerer Menge?
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Produktspezifikationen
Alle
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Memory/Memory | |
| Hersteller | Alliance Memory | |
| Verp. | FBGA-78(9x10.5) | |
| Operating Temperature | -40℃~+105℃ | |
| Features | Auto precharge function;Data mask function;Dynamic on-chip termination;ZQ calibration function;Asynchronous reset function | |
| Refresh Current | 24mA | |
| Memory Size | 8Gbit | |
| Voltage - Supply | 1.283V~1.45V;96mA | |
| Clock Frequency | 933MHz | |
| Memory Format | DDR3L SDRAM |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Memory/Memory | |
| Hersteller | Alliance Memory | |
| Verp. | FBGA-78(9x10.5) | |
| Operating Temperature | -40℃~+105℃ | |
| Features | Auto precharge function;Data mask function;Dynamic on-chip termination;ZQ calibration function;Asynchronous reset function |
| Typ | Beschreibung | |
|---|---|---|
| Refresh Current | 24mA | |
| Memory Size | 8Gbit | |
| Voltage - Supply | 1.283V~1.45V;96mA | |
| Clock Frequency | 933MHz | |
| Memory Format | DDR3L SDRAM |
Hilfe & FeedbackÄhnliche Produkte anzeigen (0) >
Merkmale
KI-Übersetzung
- Double-data-rate architecture; two data transfers per clock cycle
- The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
- Bi-directional differential data strobe (DQS and DQS) is transmitted/ received with data for capturing data at the receiver
- DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
- Differential clock inputs (CK and CK)
- DLL aligns DQ and DQS transitions with CK transitions
- Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data
- Posted CAS by programmable additive latency for better command and data bus efficiency
- On-Die Termination (ODT) for better signal quality
- Synchronous ODT
- Dynamic ODT
- Asynchronous ODT
- Multi Purpose Register (MPR) for pre-defined pattern read out
- ZQ calibration for DQ drive and ODT
- RESET pin for Power-up sequence and reset function
- SRT range : Normal/extended
- Programmable Output driver impedance control
Compliance & Exportcodes
| Typ | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Typ | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Typ | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
Alternativteile
| MPN | Hersteller | Verpackung | Verfügbarkeit | Stückpreis | ||
|---|---|---|---|---|---|---|
| AS4C1G8D3LA-10BINTR | Alliance Memory | FBGA-78(9x10.5) | 0 | $ 54.7297 | ||
| AS4C1G8D3LA-10BCN | Alliance Memory | FBGA-78(9x10.5) | 0 | $ 66.5711 | ||
| AS4C1G8D3LA-10BCNTR | Alliance Memory | FBGA-78(9x10.5) | 0 | $ 58.7693 | ||
| AS4C1G8D3LA-10BANTR | Alliance Memory | FBGA-78(9x10.5) | 0 | $ 62.6666 |

