Infineon/CYPRESS CY7C144E-55JXC

The CY7C144E is a high speed CMOS 8K×8 dual port static RAM. Various arbitration schemes are included on the CY7C144E to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C144E can be used as a standalone 64 - Kbit dual - port static RAM or multiple devices can be combined in order to function as a 16 - bit or wider master/slave dual - port static RAM. An M/S (overline) pin is provided for implementing 16 - bit or wider memory applications without the need for separate master and slave devices or additional discrete logic.

• True dual - ported memory cells that enable simultaneous reads of the same memory location
• 8Kx8 organization (CY7C144E)
• 0.35 - micron CMOS for optimum speed and power
• High - speed access: 15 ns
• Low operating power: ICC = 180 mA (typical), standby ISB = 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power - down
• TTL compatible
• Master / slave select pin enables bus width expansion to 16 - bits or more
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking between ports
• INT flag for port - to - port communication
• Available in 68 - pin PLCC and 64 - pin TQFP
• Pb - free packages available

• Interprocessor/multiprocessor designs
• Communications status buffering
• Dual - port video / graphics memory