Infineon S28HS01GTGZBHB033

This product family consists of high-speed CMOS MIRRORBIT NOR flash memory compliant with the JEDEC JESD251 expanded SPI specification. The devices are designed to meet ISO 26262, supporting ASIL-B and suitable for ASIL-D applications. Devices with an octal interface support both the Octal Peripheral Interface and the legacy Serial Peripheral Interface, both of which use sequential transaction transfers to reduce the number of interface connection signals. SPI supports single data rate, while the octal interface supports both single and double data rate. Read operations are burst-oriented, and read transactions are configurable for either wrap or linear burst mode. Wrap mode reads from a single location, while linear burst mode can read across the entire memory array. The erased state of each memory bit is logic 1; program operations can only change logic 1 to logic 0, and only erase operations can change a bit back from 0 to 1. Erase operations must be performed on an entire sector.

• 45nm MIRRORBIT technology, 2 bits stored per cell
• Address space organized in 256 KB sectors
• Configuration 1: 32 × 4KB sectors at top or bottom of address space, remaining space in full 256KB sectors
• Configuration 2: 32 × 4KB sectors equally distributed at top and bottom of address space
• 256 or 512 byte page program buffer
• 1024-bit OTP secure silicon array
• Octal interface
• JEDEC xSPI compliant
• Up to 200 MBps in single data rate mode
• Up to 400 MBps in double data rate mode
• Data strobe support for simplified read data capture on high-speed serial interfaces
• SPI interface
• JEDEC xSPI compliant
• Up to 21 MBps in single data rate mode
• Functional safety: ISO26262 ASIL B compliant and suitable for ASIL D
• Flexible endurance partitioning: partition options for high endurance or long-term data retention
• Interface CRC: detects errors in communication frames between controller and flash
• Data integrity CRC: detects errors in storage array
• Built-in ECC: single-bit error correction and double-bit error detection on array data
• Sector erase status indicator for power loss detection during erase operations
• Protection: permanent block protection for memory array and device configuration
• Protection: advanced sector protection at individual sector granularity
• Auto-boot: instant memory access after power-up
• Hardware reset via chip select pin or dedicated reset pin
• Discoverable SFDP describing device functions and features
• Device ID, manufacturer ID, identification
• Data integrity: 256 Mb device main array rated for minimum 640,000 program/erase cycles
• Data integrity: 512 Mb device main array rated for minimum 1,280,000 program/erase cycles
• Data integrity: 1 Gb device main array rated for minimum 2,560,000 program/erase cycles
• Data integrity: 4KB sectors on all devices rated for minimum 300,000 program/erase cycles
• Data integrity: minimum 25-year data retention
• Supply voltage: 1.7V ~ 2.0V
• Supply voltage: 2.7V ~ 3.6V
• Industrial temperature range: -40℃ ~ +85℃
• Industrial extended temperature range: -40℃ ~ +105℃
• Automotive temperature range per AEC-Q100 Grade 3: -40℃ ~ +85℃
• Automotive temperature range per AEC-Q100 Grade 2: -40℃ ~ +105℃
• Automotive temperature range per AEC-Q100 Grade 1: -40℃ ~ +125℃
• 256 Mb and 512 Mb device package: 24-ball BGA, 6×8mm
• 1 Gb device package: 24-ball BGA, 8×8mm