Infineon CY9BF524LPMC-GNE2

The CY9B520M Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the Arm Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, DACs and Communication Interfaces (USB, CAN, UART, CSIO, I²C, LIN).

• 32-bit Arm Cortex-M3 Core
  • Processor version: r2p1
  • Up to 72 MHz Frequency Operation
  • Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels
  • 24-bit System timer (Sys Tick): System timer for OS task management
• On-chip Memories
  • [Flash memory]
    • Dual operation Flash memory has the upper bank and the lower bank. This series could implement erase, write and read operations for each bank simultaneously.
    • Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank)
    • Work area: 32 Kbytes (lower bank)
    • Read cycle: 0 wait - cycle
    • Security function for code protection
  • [SRAM]
    • This Series on - chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I - code bus and D - code bus of Cortex - M3 core. SRAM1 is connected to System bus.
    • SRAM0: Up to 16 Kbytes
    • SRAM1: Up to 16 Kbytes
• USB Interface
  • [USB device]
    • USB2.0 Full - Speed supported
    • Max 6 EndPoint supported
      • EndPoint 0 is control transfer
      • EndPoint 1, 2 can select Bulk - transfer, Interrupt - transfer or Isochronous - transfer
      • EndPoint 3 to 5 can select Bulk - transfer or Interrupt - transfer
      • EndPoint 1 to 5 are comprised of Double Buffers.
      • Endpoint 0, 2 to 5: 64 bytes; Endpoint 1: 256 bytes
  • [USB host]
    • USB2.0 Full/Low - speed supported
    • Bulk - transfer, interrupt - transfer and Isochronous - transfer support
    • USB Device connected/dis - connected automatic detection
    • Automatic processing of the IN/OUT token handshake packet
    • Max 256 - byte packet - length supported
    • Wake - up function supported
• CAN Interface
  • Compatible with CAN Specification 2.0A/B
  • Maximum transfer rate: 1 Mbps
  • Built - in 32 message buffer
• Multi - function Serial Interface (Max eight channels)
  • 4 channels with 16 steps ×9 - bit FIFO (ch.0/1/3/4), 4 channels without FIFO (ch.2/5/6/7)
  • Operation mode is selectable from the followings for each channel:
    • UART
      • Full duplex double buffer
      • Selection with or without parity supported
      • Built - in dedicated baud rate generator
      • External clock available as a serial clock
      • Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4)
      • Various error detection functions available (parity errors, framing errors, and overrun errors)
    • CSIO
      • Full duplex double buffer
      • Built - in dedicated baud rate generator
      • Overrun error detection function available
    • LIN
      • LIN protocol Rev.2.1 supported
      • Full duplex double buffer
      • Master/Slave mode supported
      • LIN break field generation (can be changed to 13 to 16 - bit length)
      • LIN break delimiter generation (can be changed to 1 to 4 - bit length)
      • Various error detection functions available (parity errors, framing errors, and overrun errors)
    • I2C
      • Standard mode (Max 100 kbps) / Fast mode (Max 400 kbps) supported
• DMA Controller (Eight channels)
  • The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.
  • 8 independently configured and operated channels
  • Transfer can be started by software or request from the built - in peripherals
• A/D Converter (Max 26 channels) [12 - bit A/D Converter]
  • Successive Approximation type
  • Built - in 2 units
• D/A Converter (Max two channels)
• Base Timer (Max eight channels)
  • Operation mode is selectable from the followings for each channel:
    • 16 - bit PWM timer
    • 16 - bit PPG timer
    • 16 -/32 - bit reload timer
    • 16 -/32 - bit PWC timer
• General - Purpose I/O Port
  • This series can use its pins as general - purpose I/O ports when they are not used for peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.
  • Capable of pull - up control per pin
  • Capable of reading pin level directly
  • Built - in the port relocate function
• Dual Timer (32 -/16 - bit Down Counter)
  • The Dual Timer consists of two programmable 32 -/16 - bit down counters.
  • Operation mode is selectable from the followings for each channel:
    • Free - running
    • Periodic (= Reload)
    • One - shot
• Quadrature Position/Revolution Counter (QPRC) (Max two channels)
  • The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use as the up/down counter.
  • The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
  • 16 - bit position counter
  • 16 - bit revolution counter
  • Two 16 - bit compare registers